Design Verification Engineer - Accelerators

Job Title

Design Verification Engineer - Accelerators

Role Summary

Lead and execute verification strategy and infrastructure for complex computer-vision and imaging accelerator IPs and subsystems targeted for AR devices. Collaborate with architects, RTL designers, firmware/software, emulation, physical design and post-silicon teams to reach verification sign-off across multiple IPs and SoCs.

Experience Level

Senior - requires 8+ years of hands-on design verification experience and prior leadership/mentorship responsibility.

Responsibilities

Accountable for verification planning, infrastructure, and closure across accelerator IPs and subsystems.

• Define and drive verification strategy across IPs: simulation (constrained-random, UVM), formal, assertions, emulation, FPGA prototyping, and power-aware verification (UPF).
• Own DV from planning through coverage closure and sign-off for multiple complex IPs or subsystems.
• Design reusable testbench architectures, verification IP and libraries shared across IPs and SoC generations.
• Coordinate with architects, RTL, FW/SW, emulation and physical design teams to influence microarchitecture and verify integration.
• Build and scale regression management, automated triage, coverage analytics, and compute-efficient simulation/emulation runs.
• Root-cause failures to RTL, reference models or firmware/software and propose fixes.
• Identify verification-quality and productivity gaps and lead methodology and tooling improvements (including AI-assisted approaches).

Requirements

Key must-have technical skills, tools experience, and demonstrated outcomes.

• Must-have: 8+ years of verification experience with SystemVerilog, UVM and C/C++ at IP, subsystem and SoC levels.
• Must-have: Experience leading DV for complex IP or an SoC through tape-out, including owning sign-off.
• Must-have: Experience defining and executing verification plans, coverage strategies, and closure metrics (functional and code coverage) across multiple blocks.
• Must-have: Built UVM environments and reusable verification components from scratch.
• Must-have: Deep experience in at least one of: formal verification, SystemVerilog Assertions (SVA), emulation/FPGA prototyping, or low-power (UPF) verification.
• Must-have: Strong scripting skills (Python, TCL, Perl, Shell) for verification tools and flows.
• Must-have: Track record of mentoring engineers and coordinating cross-team work.
• Nice-to-have: Verified computer vision, imaging/ISP, DSP or ML accelerator designs; experience with mobile/wearable/AR SoCs; managed EDA vendors or contracted DV teams; rolled out org-wide methodology changes.

Education Requirements

Bachelor's degree in Electrical Engineering, Computer Engineering, Computer Science or a related technical field, or equivalent practical experience is expected. Master's or PhD in EE/CE/CS is listed as preferred. Equivalent practical experience is explicitly accepted.

About the Company

Company: Meta Platforms

Headquarters: Menlo Park, California, United States

American technology company that develops social networking products (Facebook, Instagram, WhatsApp) and invests in virtual/augmented reality hardware and software through Reality Labs, focusing on connectivity, advertising, and immersive computing experiences.