Design Verification Engineer

Job Title

Design Verification Engineer

Role Summary

Join the APP-LP (Analog Power Products - Linear Power) team to lead mixed-signal verification for power-management silicon. The role focuses on defining coverage-driven verification plans, building mixed-signal models and testbenches, improving verification methodology, and supporting post-silicon bring-up and debug.

Experience Level

Entry-level (1–3 years of professional experience preferred).

Responsibilities

Primary responsibilities include planning and executing verification activities, building models and testbenches, and supporting silicon debug.

• Develop coverage-driven verification plans in collaboration with system and design teams, defining analog, digital, and mixed-signal test segregation.
• Create behavioral models of analog blocks using SystemVerilog RNM / Verilog-AMS.
• Design and implement system-level AMS tests and electrical characterization scenarios for SoC top-level validation.
• Independently develop testbenches, tests, checkers, assertions, and coverage-driven randomization.
• Optimize simulation performance and debug schematic- and RTL-level failures using waveform analysis.
• Drive verification methodology improvements and work with EDA/tool teams to upgrade flows.
• Support post-silicon activities, silicon-to-simulation correlation, and customer debug.
• Collaborate cross-functionally with systems, digital, analog designers, and test/validation teams during bring-up and debug.

Requirements

Must-have technical skills and competencies for the role. Preferred tools and additional experience are listed separately.

• Strong mixed-signal fundamentals: analog building blocks, digital design processes, and top-level integration.
• Proven experience developing mixed-signal testbenches in SystemVerilog/UVM from scratch.
• Behavioral modeling experience in Verilog-AMS or equivalent for analog blocks.
• Strong simulation debug skills, including reading analog transistor-level schematics and RTL to root-cause failures.
• Ability to define system-level tests and electrical characterization scenarios for SoC verification.
• Experience developing checkers, assertions, monitors, and coverage-driven tests.
• Ability to work with cross-functional teams and support post-silicon validation and customer debug.

Nice-to-have / Preferred:

• Experience with Cadence mixed-signal tools (Virtuoso, ADE Assembler, Xcelium, VIVA, Simvision) and Spectre simulation flows.
• Advanced proficiency with SystemVerilog, UVM, Verilog-AMS; experience writing monitors and assertions for top-level simulations.
• Automation/scripting proficiency (Python, Perl, Tcl, or shell) to build regression flows and tool integrations.

Education Requirements

Bachelor's or Master’s degree in Electrical or Electronics Engineering (job listing specifies Bachelor's degree level). No alternative-equivalent-education language provided in the source.

About the Company

Company: Texas Instruments

Headquarters: Dallas, Texas, USA

Texas Instruments is a global semiconductor company that designs, manufactures, and sells analog and embedded processing chips for various markets including industrial, automotive, and personal electronics. The company's innovations aim to make electronics more affordable and reliable, fostering advancements in technology through each generation of semiconductors.