Design Verification Engineer

Job Title

Design Verification Engineer

Role Summary

Responsible for modeling and verifying complex digital and mixed-signal IP blocks used in ASIC developments. The role defines verification plans and environment architecture, develops testbenches and test cases, performs coverage analysis and closure, and debugs RTL and gate-level issues.

Works with emulation/FPGA prototyping platforms and collaborates with design teams and EDA vendors to drive adoption of advanced verification methodologies and reusable flows.

Experience Level

Senior — requires extensive experience; the posting indicates 12+ years of related verification experience (or 10+ years with an MS).

Responsibilities

Key responsibilities include:

• Define verification plans and environment architecture for block and system-level verification.
• Develop UVM-based testbenches, agents, checkers, and behavioral models.
• Create directed and constrained-random test cases and implement SystemVerilog Assertions (SVA).
• Perform coverage analysis, identify gaps, and drive coverage closure.
• Analyze and debug simulation failures at RTL and gate-level; work with netlists and SDF timing data.
• Use emulation and FPGA prototyping for verification and validation when applicable.
• Integrate tools and automation scripts to improve verification efficiency.
• Collaborate with designers and EDA vendors to resolve issues and improve flows.

Requirements

Must-have skills and experience:

• Strong experience with SystemVerilog and UVM testbench development.
• Proficient with SystemVerilog Assertions (SVA) and coverage-driven verification.
• Experience with Synopsys, Cadence, and Mentor simulation tools.
• Experience verifying complex digital and mixed-signal circuits (PLL, DLL, ADC, DAC) and analyzing analog/MXS schematics.
• Skilled at debugging RTL and gate-level netlists and analyzing SDF timing interactions.
• Familiarity with emulation platforms and FPGA prototyping workflows (helpful for responsibility scope).
• Proficient in scripting (Perl, Python, Tcl) and using version control (DesignSync, git).
• Excellent written and verbal communication skills; strong problem-solving and automation mindset.
• Ability to work independently and in global teams in a fast-paced, visible role.
• Must have legal authorization to work in the United States.

Nice-to-have:

• Hardware design and debug experience.
• Experience with emulation platforms (Palladium, Veloce, Zebu) and Xilinx FPGA prototyping.
• Formal verification experience and co-simulation skills.
• Experience with Tessent iJTAG network verification (ICL/PDL).

Education Requirements

BS in Electrical Engineering or Computer Engineering plus 12+ years of related experience; OR MS in Electrical Engineering or Computer Engineering plus 10+ years of related experience. (Degree and experience combinations are specified in the source.)

About the Company

Company: Broadcom

Headquarters: Irvine, California, United States

Broadcom is a global technology leader that designs, develops, and supplies a wide range of semiconductor and infrastructure software solutions. The company is known for its innovations in wireless and broadband communications, enabling a connected world.