Design Verification Engineer

Job Title

Design Verification Engineer

Role Summary

Work on RTL verification for complex digital designs on a hardware team based in Cupertino, CA. The role focuses on creating UVM-based tests, developing coverage and assertions, debugging failures, and collaborating with design engineers and EDA vendors to validate correctness of the RTL.

Experience Level

Mid-level. The posting does not state explicit years-of-experience guidance.

Responsibilities

The primary responsibilities are to verify RTL against design specifications, exercise corner cases, and report/track issues.

• Extract design attributes from specifications and translate them into verification requirements and test plans.
• Design and implement UVM-based tests, sequences, and constrained-random verification environments.
• Develop coverage models and assertions (SVA) to measure verification completeness and identify gaps.
• Debug failures using waveform analysis and log files; isolate root cause and report bugs to design engineers.
• Collaborate with design engineers on missing specs, corner cases, and microarchitectural behaviors.
• Integrate and use vendor IP/verification tools (VIP) and EDA tool flows in testbenches.
• Write and maintain verification infrastructure, scripts, and models; support embedded CPU verification and system modeling.
• Work a standard 40-hour work week and participate in code/review and verification process improvements.

Requirements

Must-have technical skills and experience.

• Experience with Hardware Verification and Description Languages for verification, including SystemVerilog and Verilog for verification environments.
• Practical experience with HVL/verification methodologies such as UVM, OVM, or VMM and constrained-random test development.
• Strong debugging skills for RTL issues and verification failures.
• Familiarity with reusable verification frameworks and coverage-driven verification.
• Knowledge of digital logic design, chip architecture, and microarchitecture to analyze and debug RTL.
• Experience applying AMBA protocol knowledge when developing monitors/checkers and analyzing RTL.
• SystemVerilog Assertions (SVA) for verification.
• Programming experience in C/C++ for embedded CPU verification and system modeling.
• Scripting experience in Perl or Python for testbench automation and tooling.
• Ability to define coverage spaces and write coverage models to evaluate verification quality.
• Experience working with EDA vendors and integrating VIP/tools into test benches.

Education Requirements

Master's degree (or foreign equivalent) in Electrical Engineering, Electronics Engineering, Electrical and Computer Engineering, or a related technical field. The posting frames qualifications as "Experience and/or education must include" specific verification skills; applicants with equivalent practical experience in these areas may also be considered.

About the Company

Company: Apple

Headquarters: Cupertino, California, United States

Apple is a multinational technology company that designs, manufactures, and sells consumer electronics, software, and online services. Known for its innovative products such as the iPhone, Mac computers, and iPad, Apple emphasizes a strong commitment to high-quality design and user experience.