Design Verification Engineer

Job Title

Design Verification Engineer

Role Summary

Entry-level Design Verification Engineer joining the CIP organization to verify mixed-signal power management integrated circuits. Work closely with digital, analog, and verification teams to develop verification environments, execute tests, and debug issues to improve product quality.

Position is 100% onsite in Morrisville; local candidates preferred.

Experience Level

Entry-level — New college graduate. BS with up to 2 years of experience or MS with no experience.

Responsibilities

Primary duties include developing and executing verification tests and supporting regression and debug activities.

• Collaborate with Digital, Analog, and Verification teams on system requirements.
• Participate in development of verification plans and environments.
• Develop and verify self-checking testbenches using Verilog and SystemVerilog.
• Write and execute directed and constrained-random tests to improve coverage.
• Enhance test coverage, efficiency, and overall verification effectiveness.
• Debug and report design issues; drive root-cause analysis with design teams.
• Learn and apply verification methodologies including UVM under senior guidance.
• Support regression runs and analyze simulation results.
• Document test plans, results, and findings clearly and accurately.
• Grow technical skills and contribute to team and project goals.

Requirements

Must-have technical skills and attributes for immediate contribution.

• Coursework or project experience in digital design and verification.
• Familiarity with Verilog or SystemVerilog.
• Basic understanding of analog and digital circuit concepts.
• Strong analytical, problem-solving, and debugging skills.
• Good written and verbal communication; effective team collaboration.

Nice-to-have / preferred:

• Exposure to UVM (Universal Verification Methodology) through coursework, projects, or internships.
• Understanding of power-electronics concepts (DC-DC converters, LDOs, PMICs).
• Experience with simulation tools such as Cadence Virtuoso.
• Familiarity with scripting languages such as Python or Perl.
• Familiarity with Real Number Modeling (RNM) or Verilog-AMS concepts.
• Internship or research experience in VLSI design, verification, or related fields.

Education Requirements

BS in Electrical Engineering, Computer Engineering, or a related field (acceptable with up to 2 years of experience), or MS in a related field with no prior experience. Coursework or project background in digital design/verification is expected. No certifications specified.

About the Company

Company: Renesas

Headquarters: Hitachinaka, Japan

Renesas is a global leader in embedded semiconductor solutions, providing high-quality products across automotive, industrial, infrastructure, and IoT sectors. With over 22,000 employees in more than 30 countries, the company focuses on scalable solutions that enhance user experience and drive innovation while committed to sustainability and energy efficiency.