Design Verification Design Lead - PCIe / SystemVerilog / UVM

Job Title

Design Verification Design Lead - PCIe / SystemVerilog / UVM

Role Summary

Lead pre-silicon verification for PCIe SystemC IPs and subsystems, delivering verification sign-off and high-quality verification environments. Drive verification strategy, planning, coverage closure, regression automation and cross-functional collaboration with design, architecture, modelling and validation teams.

Experience Level

Senior - 7–20 years of experience in semiconductor design verification.

Responsibilities

Primary responsibilities focus on planning and executing verification activities, ensuring coverage closure, and enabling automated regressions.

• Lead and execute pre-silicon verification for PCIe SystemC IPs and subsystems.
• Develop and maintain SystemVerilog/UVM-based verification environments and testbenches.
• Create verification plans, define strategies, and drive execution to meet KPIs and coverage targets.
• Implement functional and formal verification methodologies and drive coverage closure (functional and code coverage).
• Develop, debug, and maintain regression-ready test cases; run regressions and automate continuous regression environments.
• Analyze failures, perform root-cause analysis, and provide debug support to achieve verification sign-off.
• Prepare verification progress, KPI, and sign-off documentation.
• Collaborate with design, architecture, modelling and validation teams and support verification environment qualification.
• Contribute to automation and tooling (Jenkins, scripting) and support Certitude/formal closure activities.

Requirements

Must-have skills first, followed by concise nice-to-have items.

• 7–20 years of semiconductor design verification experience.
• Strong hands-on experience with SystemVerilog and UVM.
• Proven experience in constraint-random functional verification and verification planning.
• Experience with formal verification methodologies.
• Experience in PCIe IP/subsystem verification and SystemC at IP/subsystem level.
• Testbench development, regression management, debugging and coverage-closure experience.
• Regression automation experience using Jenkins and scripting (Python, Perl).
• Hands-on use of verification tools such as Xcelium and Vmanager Enterprise Edition.
• Strong analytical, debugging, problem-solving skills and effective English communication.

Nice-to-have:

• Familiarity with Specman e (or willingness to learn).
• Mixed-signal IP verification experience using RNM / Verilog-A.
• C modelling for digital signal blocks and MATLAB modelling experience.
• Knowledge of VHDL.
• Knowledge of functional safety (ISO 26262).
• Experience with Certitude and formal/functional verification closure.

Education Requirements

Not specified.

About the Company

Company: Anlage Infotech

Headquarters: Bengaluru, Karnataka, India

Anlage Infotech is an engineering services company providing semiconductor design and verification, embedded systems, and software solutions. They offer expertise in pre-silicon verification, IP/subsystem verification, and related tools and methodologies for global semiconductor and electronics clients.