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Design Verification Architect / Director

Cadence Design Systems
July 29, 2026
Full-time
On-site
San Jose, California, United States
$178,500 - $331,500 USD yearly
Verification Jobs, Level - Senior

Job Title

Design Verification Architect / Director

Role Summary

Lead the Processor Verification team responsible for verification of microprocessor cores and their peripherals. The role owns verification planning, testbench implementation, coverage collection and closure, and cross-functional coordination with architecture, design, and firmware teams.

Manage and track the work of a team (~7–10 engineers) to deliver thorough verification of complex CPU designs.

Experience Level

Senior level β€” requires extensive experience. The posting specifies 17+ years of design verification experience.

Responsibilities

Own verification strategy and execution for CPU cores and memory subsystems; implement and run simulation/emulation and diagnostics to achieve closure.

  • Develop and execute verification plans for complex in-order/out-of-order CPU cores and associated peripherals.
  • Design and implement simulation or emulation testbenches, UVM components, assertions, coverage monitors, and assembly/C diagnostics.
  • Collect, track, and drive coverage closure; define coverage scope with cross-functional teams (DV/Arch/Design/FW).
  • Manage and report progress for a team of approximately 7–10 engineers.
  • Integrate automated verification flows, gate-level simulations, and formal verification where applicable.

Requirements

Must-have technical skills, management experience, and communication ability required to lead processor verification efforts.

  • 17+ years of design verification experience, with strong knowledge of computer architecture and verification fundamentals.
  • Proven experience leading and managing engineering teams.
  • Expertise in SystemVerilog and UVM to build flexible, reusable complex testbenches.
  • Experience with assembly language programming.
  • Familiarity with scripting (Perl, Unix shell, or similar) to support verification flows.
  • Experience developing fully automated verification flows and conducting gate-level simulations.
  • Working knowledge of coverage collection and closure processes; ability to collaborate across DV/Arch/Design/FW.
  • Strong written and oral communication skills.
  • Formal verification experience is a plus.

Education Requirements

BS or higher in Electrical Engineering or Computer Engineering (posting states "BS (or higher) in EE/Computer Engineering").


About the Company

Company: Cadence Design Systems

Headquarters: San Jose, California, USA

Cadence Design Systems is a global electronic design automation company that provides software, hardware, and intellectual property for designing advanced semiconductor chips. With over 25 years in the industry, Cadence is known for its innovative technology solutions and has been recognized by Fortune Magazine as one of the 100 Best Companies to Work For. The company is dedicated to solving complex technical challenges in order to enable customers to create revolutionary products and experiences.

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Date Posted: 2026-07-28