Design Methodology – Principal DRAM Power Integrity Engineer

Job Title

Design Methodology 6 Principal DRAM Power Integrity Engineer

Role Summary

Principal engineer on the design methodology team responsible for EMIR (electromigration / IR) and PDN (power-delivery-network) analysis for DRAM products. Owns methodology, tooling, analysis flows, and signoff support while coordinating across design, physical implementation, timing, modeling, verification, and EDA vendors.

Experience Level

Senior-level role. Target experience: approximately 814 years in PDN / Power Integrity / EMIR analysis for advanced semiconductor or SoC designs.

Responsibilities

The role focuses on establishing and executing robust EMIR methodology and driving closure to signoff across multiple DRAM designs.

• Develop and standardize EMIR/PDN methodology and Best Known Methods (BKMs) across DRAM products.
• Perform static and dynamic EM/IR and PDN analysis using RedHawk, Totem, or equivalent tools; debug and provide actionable recommendations to design/layout teams.
• Use AI-assisted tools, agentic workflows, and automation frameworks to improve analysis throughput and accuracy.
• Maintain and validate the end-to-end EMIR flow: netlist prep, extraction, simulation, debug, reporting, and silicon correlation across operating modes and temperatures.
• Partner with design, timing, PnR, architecture, modeling, verification teams, and EDA vendors to align expectations and develop worst-case scenarios.
• Create and maintain dashboards and metrics to track EMIR results, trends, and signoff progression for multiple designs.
• Support chip-level signoff and tapeout readiness for DRAM products.

Requirements

Must-have technical skills and experience to perform the role effectively. Nice-to-have items are listed after required items.

• 814 years of experience in PDN / Power Integrity / EMIR analysis for advanced semiconductor or SoC designs.
• Hands-on experience with Ansys RedHawk or Totem (or equivalent) for full-chip EM/IR verification, including setup, scenario creation, debug, and root-cause analysis.
• Expertise in vectorless and dynamic/pattern-based IR-drop analysis; strong ability to interpret switching activity, current behavior, and voltage-sensitivity trends.
• Proven ability to identify IR-drop root causes (grid resistance, parasitics, routing topology, switching activity) and recommend design/layout fixes.
• Experience performing SoC/chip-level EMIR signoff and supporting tapeouts.
• Solid understanding of PDN interactions with timing/margin, layout topology, and chip-level power architecture.
• Familiarity with automation frameworks (Make or similar) for EMIR rollups and data processing.
• Hands-on experience with low-power, multi-voltage, power-off, or mixed-signal designs and driving cross-functional closure.
• Ability to work with EDA vendors and cross-geography teams to improve methodologies and correlate to silicon.

Nice-to-have:

• Power-modeling or current-source modeling experience (e.g., CPM).
• Scripting skills in Python or Tcl for automation and data analysis.
• Knowledge of PnR or STA tools (e.g., FusionCompiler, PrimeTime) and SPICE/circuit-design background.
• Exposure to AI/ML-assisted design flows or interest in advanced automation.
• Familiarity with memory-product power behavior (DRAM/SRAM/NAND).

Education Requirements

Master's degree in Electrical Engineering or Computer Engineering (explicitly stated). No other degree or equivalent-experience language was provided in the posting.

About the Company

Company: Micron Technology

Headquarters: Boise, Idaho, USA

Micron Technology is a global leader in memory and storage solutions, dedicated to transforming how the world uses information. The company offers a diverse portfolio of high-performance DRAM, NAND, and NOR memory products under the Micron and Crucial brands. With a commitment to customer focus and technological innovation, Micron drives advancements in artificial intelligence, 5G, and other data-centric applications, empowering users to learn, communicate, and progress.