Design Methodology – Principal DRAM Power Integrity Engineer

Job Title

Design Methodology – Principal DRAM Power Integrity Engineer

Role Summary

Lead development and standardization of EM/IR (EMIR) and power‑delivery‑network (PDN) methodology for DRAM products. Perform full‑chip EM/IR and PDN analysis, drive root‑cause identification and mitigation, and partner with design, layout, verification, and EDA vendors to improve analysis flows and signoff consistency.

Experience Level

Senior level. The role expects experienced engineers with substantial domain experience (the posting lists 8–14 years of PDN / Power Integrity / EMIR analysis experience).

Responsibilities

Primary responsibilities include setting methodology, executing analysis, and coordinating cross‑functional closure.

• Develop and standardize EMIR methodology across DRAM product lines to ensure repeatable, high‑quality analysis and signoff criteria.
• Perform static and dynamic EM/IR and PDN analysis using industry tools (e.g., RedHawk, Totem), identify root causes such as high resistance, insufficient vias, or decap gaps, and provide actionable fixes.
• Use and integrate AI‑assisted tools, agentic workflows, and automation frameworks to scale PDN analysis and diagnosis.
• Maintain the end‑to‑end EMIR flow: netlist preparation, extraction, simulation, debug, reporting, and silicon correlation across operating modes and temperatures.
• Partner with design, timing, physical implementation, architecture, modeling, and verification teams to develop worst‑case vectors and align analysis expectations.
• Collaborate with global teams and EDA vendors to evaluate and improve tools and document Best Known Methods (BKMs).
• Develop dashboards and metrics to track EMIR results, monitor trends, and support signoff progression for multiple designs.

Requirements

Concise list of required technical skills and relevant experience.

• Deep hands‑on experience with Ansys RedHawk, Totem, or equivalent full‑chip EM/IR verification and PDN analysis tools (setup, scenario creation, debug, root‑cause analysis).
• Expertise in vectorless and dynamic/pattern‑based IR‑drop analysis and the ability to interpret switching behavior, current profiles, and voltage‑sensitivity trends.
• Proven ability to identify IR‑drop root causes (switching activity, grid resistance, parasitics, routing topology) and recommend design/layout fixes.
• Experience performing SoC/chip‑level EMIR signoff and supporting tapeouts, and driving closure across multi‑functional teams.
• Solid understanding of PDN interactions with timing, layout topology, and chip power architecture; familiarity with end‑to‑end design flow (RTL to silicon correlation).
• Familiarity with Make or similar automation frameworks for EMIR rollups; experience with low‑power, multi‑voltage, power‑off, or mixed‑signal designs.

• Power‑modeling or current‑source modeling experience (e.g., CPM).
• Scripting for automation and data analysis (Python, Tcl).
• Experience improving EMIR/PI analysis flows or methodology and familiarity with PnR/STA tools (FusionCompiler, PrimeTime).
• Background in circuit design and SPICE simulation; exposure to AI/ML‑assisted design flows and memory‑product power behavior (DRAM/SRAM/NAND).

Education Requirements

Master's degree in Electrical Engineering or Computer Engineering (explicitly stated in the posting).

About the Company

Company: Micron Technology

Headquarters: Boise, Idaho, USA

Micron Technology is a global leader in memory and storage solutions, dedicated to transforming how the world uses information. The company offers a diverse portfolio of high-performance DRAM, NAND, and NOR memory products under the Micron and Crucial brands. With a commitment to customer focus and technological innovation, Micron drives advancements in artificial intelligence, 5G, and other data-centric applications, empowering users to learn, communicate, and progress.