Design Layout Engineer
Design Layout Engineer on the HBM team in Guadalajara responsible for creating and delivering high-quality analog, mixed-signal and custom-digital layouts for High Bandwidth Memory projects. Works across Micron's global engineering teams on multiple concurrent projects to meet schedule and integration targets.
Focus on layout implementation, verification (LVS/DRC/antenna), documentation, and coordination to support AI and high-performance computing applications.
Mid-level β approximately 5 years of relevant analog/custom layout design experience in CMOS processes including Planar and FinFET nodes.
Primary duties include block-level and full-chip layout implementation, verification, and project coordination.
Must-have technical skills and experience.
Nice-to-have:
BE or MTech in Electronics/VLSI Engineering or a related technical field (specified in the posting).
Company: Micron Technology
Headquarters: Boise, Idaho, USA
Micron Technology is a global leader in memory and storage solutions, dedicated to transforming how the world uses information. The company offers a diverse portfolio of high-performance DRAM, NAND, and NOR memory products under the Micron and Crucial brands. With a commitment to customer focus and technological innovation, Micron drives advancements in artificial intelligence, 5G, and other data-centric applications, empowering users to learn, communicate, and progress.
