Job Title
Design For Test Engineer III (IC)
Role Summary
Responsible for implementing and validating DFT for advanced SoC designs (3nm and 5nm), focusing on IP-level and top-level DFT, test pattern generation, simulation, and silicon bring-up. Works as part of an engineering services team supporting networking and consumer SoCs.
Experience Level
Mid-level. 5β7 years of experience in design-for-test (DFT) engineering, particularly on large SoCs.
Responsibilities
Key duties include:
- Implement DFT for 3nm and 5nm networking SoCs and IPs.
- Perform RTL checks for scan-insertion compatibility using Synopsys Spyglass.
- Execute scan-insertion and compression using Mentor Tessent TestKompress.
- Generate ATPG patterns (compressed and uncompressed) using Tessent, Cadence Modus, or Synopsys Tetramax.
- Run pattern simulations with and without timing across corners using VCS.
- Debug mismatches using Verdi and support silicon debug/bring-up at block and top levels.
- Insert and verify MBIST and IEEE 1149.1 JTAG on blocks and top.
- Automate and enhance DFT flows and makefiles using Perl, Shell, Tcl and DAeRT processes.
- Collaborate with design, validation and silicon teams; travel to client office as required.
Requirements
Must-have technical skills and experience:
- 5β7 years of DFT experience working on multi-million gate SoCs (networking, consumer) and IPs such as PLL and SerDes.
- Hands-on experience with scan-insertion, ATPG, GLS, and pattern simulation (with and without timing).
- MBIST insertion and verification experience.
- Experience with IEEE 1149.1 (JTAG) insertion and verification.
- Scripting proficiency in Perl, Shell and Tcl for flow automation.
- Familiarity with Mentor Tessent; exposure to Cadence Modus and Synopsys Tetramax preferred.
- Experience with VCS for simulation and Verdi for debug.
- Strong communication skills and ability to work on-site with clients.
- Knowledge of low-power DFT techniques.
Education Requirements
B.Tech or M.Tech in Microelectronics, Electronics or a closely related field (as stated in the source).
About the Company
Company: eInfochips
Headquarters: Bengaluru, India
eInfochips is a product engineering and semiconductor design services company offering embedded software, SoC design and verification, testing, and IoT solutions. It operates as part of Arrow Electronics, serving clients across industries worldwide.

Date Posted: 2026-07-22