Design For Test Engineer (DFT)
QualcommJob Title
Design For Test Engineer (DFT)
Role Summary
The DFT engineer will design, implement and validate design-for-test and design-for-debug solutions for complex, low-power, high-performance ASIC/SoC projects. The role sits in the ASIC engineering organization and works with cross-functional teams (design, verification, validation, manufacturing) to define test strategy, enable silicon bring-up and improve production yield.
Experience Level
Mid-level — typical candidate has multiple years of ASIC/DFT experience (see Education Requirements for degree and years guidance).
Responsibilities
Primary responsibilities focus on DFT/DFD methodology deployment and silicon validation for production-ready SoCs.
- Design and implement advanced DFT/DFD techniques for low-power, high-performance SoCs.
- Develop and deploy test methodologies (scan, ATPG, MBIST, JTAG, scan compression) to reduce test cost and improve production quality and yield learning.
- Integrate scan insertion and DFT flows into the RTL-to-GDSII toolchain.
- Support silicon bring-up and debug of DFT features on ATE and collaborate with validation and manufacturing teams.
- Work with cross-functional teams to define test strategy, fault models and at-speed testing requirements.
Requirements
Must-have technical skills and experience.
- Hands-on ASIC design, verification, or related engineering experience (industry experience on ASIC/SoC projects).
- Strong knowledge of DFT/DFD techniques, core-based test methodology and scan isolation.
- Familiarity with fault models (stuck-at, transition, path delay, gate-exhaustive, IDDQ) and fault simulation concepts.
- Practical experience with ATPG and test tools (examples: Synopsys Tetramax, Cadence Encounter Test, Siemens Tessent).
- Experience with scan insertion tools/flows (e.g., Synopsys DFTCompiler or Fusion Compiler scan insertion).
- Direct experience in silicon bring-up, ATE debug and validation of DFT features.
- Experience with RTL design and verification (VHDL/Verilog), synthesis and static timing analysis.
- Experience with industry simulators (e.g., VCS, Modelsim) and scripting (TCL, Python, or Perl).
Nice-to-have:
- Experience with formal verification tools (LEC, Formality).
- Experience with low-power design methodologies and UPF tools; familiarity with low-power verification tools (e.g., Conformal Low Power).
Education Requirements
Bachelor's degree in Science, Engineering, or a related field with 4+ years of relevant ASIC/DFT experience; OR Master's degree in Science, Engineering, or a related field with 3+ years' experience; OR PhD in Science, Engineering, or a related field with 2+ years' experience. Applications with equivalent practical experience will be considered.
About the Company
Company: Qualcomm
Headquarters: San Diego, California, United States
Qualcomm is a global leader in semiconductor and telecommunications equipment, specializing in mobile technologies and innovations. Known for its Adreno GPUs, the company provides solutions enabling advancements in mobile gaming, AI, VR/AR, and autonomous driving. Qualcomm's cutting-edge technology and commitment to high-performance, power-efficient designs drive the evolution of mobile graphics and connectivity worldwide.
