Design for Test Engineer

Job Title

Design for Test Engineer

Role Summary

Work on Design-for-Test (DFT) implementation and test pattern generation for ASIC/hardware projects. The role collaborates with front-end, verification (DV), physical design (PD), static timing (STA) and CAD teams to ensure high-quality scan insertion and ATPG flows across the design cycle.

Primary goals are to enable reliable scan insertion during RTL/synthesis, improve ATPG coverage and flow robustness, and support debug of simulation and silicon failures.

Experience Level

Entry-level / Early career. Typically requires about 2 years of relevant industry experience.

Responsibilities

Execute and maintain DFT flows and provide operational support to cross-functional teams during design and verification phases.

• Perform scan insertion and ATPG during the DFT development phase.
• Deliver configuration files and automation scripts used by front-end RTL generation for scan insertion.
• Debug and resolve scan insertion issues that arise during synthesis and collaborate with front-end engineers on fixes.
• Support PD, STA and DV teams on issues caused by scan insertion and ensure design compliance with timing, power and logical requirements.
• Maintain and improve ATPG flows to achieve higher stuck-at coverage; generate partition-level and top-level patterns per project targets.
• Work with CAD teams and tool vendors to resolve tool issues and improve automation and flows.
• Investigate simulation and silicon failures and implement fixes via RTL, scripts, or configuration changes; implement ECOs as needed.
• Create infrastructure and checks to catch RTL/DFT issues earlier in the design cycle.

Requirements

Core technical skills required for immediate contribution.

• Proficient in Verilog for DFT IP development.
• Experience with RTL DFT features such as scan codec, ATPG isolation, and scan routing.
• Scripting skills in Python, Perl, or Tcl for automating design, verification and synthesis flows.
• Familiarity with front-end verification tools (CDC, RDC, Lint) and ability to resolve clock/reset domain issues.
• Experience with synthesis tools, including setting up constraints and configurations.
• Hands-on experience with ATPG tools for Scan DRC, coverage analysis and improvement.
• Working knowledge of computer architecture principles and basic SoC development flows to enable DFT analysis and debug.
• Understanding of scan and MBIST DFT architecture and implementation concepts.

Nice-to-have: Not specified.

Education Requirements

Master’s degree or foreign equivalent in Electrical Engineering, Electronics Engineering, or a related field. The posting specifies 2 years of experience in the job offered or a related occupation.

About the Company

Company: Apple

Headquarters: Cupertino, California, United States

Apple is a multinational technology company that designs, manufactures, and sells consumer electronics, software, and online services. Known for its innovative products such as the iPhone, Mac computers, and iPad, Apple emphasizes a strong commitment to high-quality design and user experience.