Design for Test (DFT) Engineer – RTL & Test Chip Architecture

Job Title

Design for Test (DFT) Engineer – RTL & Test Chip Architecture

Role Summary

Experienced DFT engineer responsible for RTL-based DFT implementation, test-chip architecture, and silicon validation for advanced ASIC/SoC designs. The role spans DFT architecture definition, scan and memory BIST strategies, ATPG/pattern generation, and support for silicon bring-up and production test.

Works closely with RTL design, verification, physical design, product engineering and ATE teams to ensure manufacturable, testable silicon for volume production.

Experience Level

Mid-level (5–12 years of relevant DFT/ASIC experience).

Responsibilities

Design, implement and verify DFT features from RTL through silicon; support production test and yield improvement.

• Define and implement scalable DFT architecture for complex SoC/ASIC designs.
• Develop and integrate scan chains, scan compression, MBIST/LBIST, boundary-scan (JTAG), and IEEE 1500/1687 test infrastructures.
• Perform DFT insertion, verification and signoff using industry EDA tools.
• Generate and optimize ATPG patterns to maximize fault coverage while minimizing test time and tester memory.
• Support RTL teams to implement test-friendly architectures and resolve DFT issues.
• Collaborate with Physical Design on scan reordering, clocking, timing closure and DFT-aware floorplanning.
• Support silicon bring-up, characterization, ATE integration, and production test flows; debug scan failures and test escapes.
• Develop reusable DFT IP, automation scripts, and methodologies for future programs.
• Review test coverage reports, fault models and quality metrics to ensure manufacturing readiness across multiple tape-outs.

Requirements

Must-have technical skills and practical experience relevant to DFT and production test.

• 5–12 years hands-on experience implementing DFT for ASIC or SoC designs (scan, ATPG, MBIST/LBIST, test-chip architecture).
• Strong RTL DFT implementation skills (Verilog/SystemVerilog) and understanding of RTL-to-silicon design flow.
• ATPG and fault coverage experience (stuck-at, transition, cell-aware test); pattern validation and test time optimization.
• Experience with silicon bring-up, production test, ATE interaction and root-cause debug of manufacturing defects.
• Familiar with EDA DFT tools such as Synopsys DFT Compiler, Tessent, TestMAX, Modus, SpyGlass DFT, DFTPrimeTime.
• Automation and scripting skills: Tcl, Perl, Python, shell scripting.
• Ability to produce DFT documentation, guidelines and reusable IP for program scaling.

Nice-to-have:

• Experience with physical implementation tools (Design Compiler, ICC2) and low-power design considerations.
• Previous work on test-chip architecture and ATE characterization for advanced process nodes.

Education Requirements

Bachelor's or Master's degree in Electronics, Electrical Engineering, Computer Engineering or a related technical discipline required (or equivalent technical experience).

About the Company

Company: Best NanoTech

Headquarters: Bengaluru, Karnataka, India

Best NanoTech appears to be a semiconductor/VLSI company hiring for DFT (Design for Test) engineers to work on RTL-based DFT implementation, test chip architecture, scan design, ATPG, MBIST/LBIST, silicon validation and production test for ASIC/SoC designs.