Design for Test (DFT) Engineer
VoltaiJob Title
Design for Test (DFT) Engineer
Role Summary
Own DFT architecture and implementation for SoCs and IP, ensuring chips are testable in manufacturing and in the field. Work on production tapeouts with semiconductor partners and integrate DFT flows with verification, physical design, and test engineering.
Experience Level
Mid-level. The role requires 5+ years of DFT experience on production tapeouts.
Responsibilities
Primary responsibilities include DFT architecture, insertion, verification, and supporting silicon bring-up and test automation.
- Define DFT architecture (scan, compression, MBIST, LBIST, boundary scan) for SoCs and IP.
- Insert and verify DFT logic and generate ATPG patterns to meet coverage targets.
- Collaborate with RTL, synthesis, and physical design teams to address DFT timing and area impact.
- Support silicon bring-up, pattern debug, and yield analysis with test and product engineering.
- Build automation for DFT flows and coverage reporting.
- Collaborate on integrating AI to accelerate DFT insertion and pattern generation.
Requirements
Must-have technical skills and tools followed by desirable experience.
- Must-have: 5+ years of DFT experience on production tapeouts.
- Hands-on experience with Tessent, TestMAX, or Modus.
- Strong knowledge of scan, compression, ATPG, MBIST, and IEEE 1149.1/1687.
- Experience with DFT verification and gate-level simulation.
- Proficient in Tcl and Python scripting.
- Nice-to-have: post-silicon test bring-up and ATE experience; experience with 2.5D/3D or chiplet test strategies; interest in AI-assisted design tools.
Education Requirements
Not specified.
About the Company
Company: Voltai
Headquarters: Palo Alto, CA, United States
Voltai develops AI-driven world models and agents to design, evaluate, and optimize physical systems-focusing on hardware, electronics, and semiconductors to enable AI-led hardware co-design, performance modeling, and cross-domain optimization.
