Design-for-Test (DFT) Engineer - ASIC Backend (Associate / Experienced / Lead)

Job Title

Design-for-Test (DFT) Engineer - ASIC Backend (Associate / Experienced / Lead)

Role Summary

Join Boeing Electronic Products as a DFT engineer on the ASIC backend team supporting advanced digital subsystems for aerospace products. The role designs, verifies, and validates on-chip test infrastructure (scan, MBIST, JTAG/IJTAG, scan compression) and supports post-silicon debug and bring-up.

Work with chip design, verification, and cross-functional teams to integrate DFT features across the design flow; position is expected to be onsite in El Segundo or Huntington Beach, CA.

Experience Level

Open across multiple levels: Associate (approx. 2+ years), Experienced (approx. 5+ years), Lead (approx. 9+ years). Hiring level will be adjusted by candidate experience.

Responsibilities

Primary technical responsibilities include designing DFT architectures, generating test patterns, validating memory/test infrastructure, and supporting silicon bring-up.

• Design and implement DFT architectures: TAP/JTAG, IJTAG (IEEE 1687), Boundary Scan (BSCAN), MBIST, and scan compression.
• Develop and validate TAP/JTAG and IJTAG infrastructures and create BSDL/ICL/PDL artifacts.
• Drive ATPG pattern generation, pattern coverage optimization, and memory test validation.
• Perform silicon debug: scan testing, at-speed testing, and bring-up support.
• Integrate DFT features into the chip design flow and collaborate with design, verification, and manufacturing teams.
• Coordinate with external partners/customers on custom DFT interfaces and security requirements when applicable.
• Contribute to development and deployment of DFT methodologies for next-generation products.
• Occasional travel and after-hours meetings during critical milestones.

Requirements

Must-have technical skills, security and eligibility requirements, and practical experience for the role. Education details are summarized under Education Requirements below.

• Ability to obtain a U.S. security clearance; U.S. Citizenship/U.S. Person status required for export-control compliance.
• Practical DFT experience (role-adjusted): minimum ~2 years for Associate level; higher for Experienced/Lead levels.
• Strong knowledge of ASIC/logic design flow, HDL (Verilog/SystemVerilog), static timing analysis, and ECO processes.
• Hands-on experience with TAP/JTAG, IJTAG (IEEE 1687), Boundary Scan (IEEE 1149.1), MBIST, scan compression, ATPG, at-speed test, and silicon debug.
• Proficiency in scripting for DFT automation and verification (Tcl, Perl, Python).
• Experience with DFT verification methodologies and pattern generation/coverage optimization.
• Good analytical, problem-solving, and communication skills; ability to coordinate across teams and with external partners.
• Nice-to-have: FPGA implementation experience, timing closure, CDC/timing fundamentals, verification collaboration, high-speed interfaces, SoC/memory integration, mentoring or technical leadership exposure.

Education Requirements

Required: Bachelor of Science in Engineering (Electrical, Mechanical, Aeronautical), Computer Science, Data Science, Mathematics, Physics, Chemistry, or non‑US equivalent; Bachelor’s or Master’s in EE, Computer Engineering/Science or related field is listed as preferred. The posting allows equivalent combinations of technical education and experience (e.g., experience in lieu of degree). ABET accreditation is preferred but not required.

About the Company

Company: Boeing

Headquarters: Arlington, Virginia, United States

Large U.S. aerospace and defense company that designs, manufactures, and services commercial airplanes, military aircraft, satellites, and related systems and services worldwide.