Design for Test (DfT) Architect

Job Title

Design for Test (DfT) Architect

Role Summary

The DfT Architect defines and governs the Design-for-Test strategy and architecture for complex SoCs and IP, coordinating system architecture, design, verification, physical design, product engineering and test engineering to ensure manufacturable, testable products.

Drives scalable, reusable DfT solutions, influences technical direction across projects, and mentors engineers and architects to meet test quality, cost and schedule targets.

Experience Level

Senior — typically requires 15+ years of semiconductor development experience with proven DfT leadership.

Responsibilities

Responsibilities span strategy, technical leadership, production readiness, methodology and team development:

• Define DfT strategy and architectures for digital, memory and analog SoCs and IP.
• Create and maintain the DfT specification and testability acceptance criteria.
• Drive architectural decisions balancing quality, cost, test time and schedule; assess impact of specification and design changes.
• Act as technical lead for DfT implementation teams; align architects, designers, verification and product/test engineers.
• Review designs for compliance with DfT requirements and resolve complex architectural trade-offs.
• Define fault modelling and coverage strategy; guide test concepts to achieve target quality levels.
• Support silicon bring-up, characterization, production ramp and root-cause analysis of field/production failures.
• Develop and deploy new DfT methodologies, drive standardization and reuse, and influence EDA tool roadmaps and automation.
• Coach and mentor DfT engineers and emerging architects; contribute to hiring and technical career development.

Requirements

Must-have skills and experience; listed concisely:

• 15+ years experience in semiconductor development with proven experience as a DfT Architect, Lead Engineer or Technical Lead.
• Proven track record delivering complex SoC products from concept through production.
• Deep experience with scan architecture, ATPG, test compression, JTAG, IEEE1687 and IEEE1149.x.
• Practical knowledge of memory BIST, logic BIST, analog/mixed-signal DfT, fault modelling, silicon debug and production test development.
• Familiarity with automotive quality methodologies, yield/DPPM prediction and test cost considerations.
• Experience with RTL design and verification flows and modern EDA toolchains (Synopsys, Cadence, Siemens).
• Strong strategic thinking, systems perspective, technical influencing, stakeholder management, and mentoring capabilities.

Education Requirements

MSc or PhD in Electrical Engineering, Computer Engineering or a related discipline.

About the Company

Company: NXP Semiconductors

Headquarters: Nijmegen, Netherlands

NXP Semiconductors N.V. is a global semiconductor company that provides High Performance Mixed Signal and Standard Product solutions. With over 45,000 employees and operations in more than 35 countries, NXP is a leader in secure connectivity solutions for embedded applications, catering to automotive, industrial IoT, mobile, and communication infrastructure markets. The company is committed to innovation and sustainability, advancing a smarter, safer, and more sustainable world through technology.