Design Engineer - STA

Job Title

Design Engineer - STA

Role Summary

Work on chip-level static timing analysis (STA) and timing signoff for advanced CMOS ASICs in Broadcom's Custom Silicon Design Team in Fort Collins, CO. The role covers timing architecture, analysis, closure, and methodology for high-performance SoCs targeting AI, networking, storage, and compute applications.

Experience Level

Senior-level role. The posting specifies experience expectations tied to degree (see Education Requirements).

Responsibilities

Primary responsibilities include timing definition, analysis, closure, and automation across design flows and process corners.

• Develop, validate, and maintain timing constraints for complex SoC designs across multiple modes and corners.
• Perform static timing analysis using tools such as Synopsys PrimeTime or Cadence Tempus.
• Define and execute timing signoff methodologies, including process corners, derates, and uncertainties.
• Conduct pre- and post-route timing analysis, QoR evaluations, and closure verification.
• Generate and validate timing ECOs to achieve signoff-quality closure across PVT corners.
• Automate timing flows and analysis using Tcl and scripting languages (Python, Perl, etc.).
• Collaborate with physical design, synthesis, and clock teams to ensure timing convergence and cross-domain consistency.
• Analyze and debug timing violations, signal integrity issues, and clock network challenges.
• Support power and performance optimization via timing analysis and constraint tuning.
• Ensure compliance with timing signoff checklists, methodology, and documentation.

Requirements

Technical and practical skills required to perform STA and timing signoff for advanced ASIC designs.

• Must-have: Strong VLSI and ASIC physical design fundamentals; proven STA experience and timing-closure track record.
• Must-have: Hands-on experience with industry STA tools (Synopsys PrimeTime and/or Cadence Tempus) and Linux/UNIX environments.
• Must-have: Proficiency with Tcl scripting; experience automating timing flows.
• Must-have: Strong understanding of setup/hold analysis, multi-mode multi-corner (MMMC) timing, ECO convergence, and clock network principles.
• Preferred: Proficiency in Python, Perl, or Ruby for analysis and automation.
• Preferred: Exposure to advanced STA techniques (POCV/SOCV/LVF, PBA), SPICE correlation, timing libraries (CCS/ECSM/NLDM), and MIS effects.
• Preferred: Experience working on advanced process nodes (3 nm and below) and high-frequency SoC designs.
• Strong communication, analytical, and mentoring skills; ability to work with cross-functional and global teams.

Education Requirements

BS in Electrical or Computer Engineering with 8+ years of relevant experience, or MS in Electrical or Computer Engineering with 6+ years of relevant experience.

About the Company

Company: Broadcom

Headquarters: Irvine, California, United States

Broadcom is a global technology leader that designs, develops, and supplies a wide range of semiconductor and infrastructure software solutions. The company is known for its innovations in wireless and broadband communications, enabling a connected world.