Design Engineer - STA

Job Title

Design Engineer - STA

Role Summary

Member of the static timing analysis (STA) team responsible for timing closure and timing signoff for ASIC/VLSI designs. Works with RTL, synthesis and physical design teams to create and validate timing constraints and reports.

Role requires independent problem solving, cross-team coordination across time zones, and handling complex timing/debugging tasks for advanced designs.

Experience Level

Senior level — role expects a highly experienced engineer (10+ years of relevant STA/physical design experience based on required degree/experience combinations).

Responsibilities

Primary responsibilities focus on STA delivery, timing closure, and cross-team coordination.

• Perform static timing analysis and signoff using industry tools (e.g., Synopsys PrimeTime, Cadence Tempus).
• Create, debug and maintain timing constraints and timing scripts (TCL).
• Generate, analyze and explain timing reports; resolve timing violations (setup, hold, false paths, etc.).
• Model and analyze effects of RC networks, crosstalk, signal integrity, and noise on timing.
• Support timing for advanced packaging/3DIC designs and perform SPICE-based analysis when needed.
• Coordinate with synthesis, place-and-route, verification and circuit teams across locations and time zones.
• Organize and present large data sets and debug complex timing issues to propose engineering solutions.
• Provide technical leadership on special assignments and may supervise junior engineers.

Requirements

Core technical skills and practical STA experience required. Preferred skills noted where applicable.

• Must-have: Strong understanding of VLSI and ASIC physical design; familiarity with flip-flops, latches, memories and CMOS logic.
• Must-have: Hands-on experience with static timing analysis tools (Synopsys PrimeTime and/or Cadence Tempus) and ability to interpret warnings/errors and timing reports.
• Must-have: Ability to create and debug timing constraints and timing diagrams; solid understanding of setup and hold analysis.
• Must-have: Proficient in TCL for STA scripting.
• Preferred: Experience with Python, Ruby or Bash for automation.
• Preferred: Knowledge of advanced STA topics: POCV/SOCV/LVF variation modeling, MIS, CCS/ECSM/NLDM liberty timing models, PBA, LOCV/SOCV derates.
• Preferred: Experience with timing for SOIC/3DIC designs and SPICE analysis.
• Other: Strong communication, organization and multi-tasking skills; ability to work across global teams and manage large datasets.

Education Requirements

BS in Electrical Engineering or Computer Engineering with 12+ years related experience, or MS in Electrical Engineering or Computer Engineering with 10+ years related experience (degree plus specified years required per posting).

About the Company

Company: Broadcom

Headquarters: Irvine, California, United States

Broadcom is a global technology leader that designs, develops, and supplies a wide range of semiconductor and infrastructure software solutions. The company is known for its innovations in wireless and broadband communications, enabling a connected world.