Design Engineer - Physical Design
Work on physical implementation of high-speed digital DDR PHY IP for advanced process nodes (TSMC 2nm–12nm, Samsung 2nm–10nm). The team delivers high-performance products with frequencies up to 8800MHz and addresses challenges in floorplanning, clock tree synthesis, and timing closure.
Develop scripts and tools to improve PD design flow, optimize PPA, and implement robust flows across product projects.
Mid-level. Typical experience expected: approximately 2–4+ years in physical design engineering focused on digital implementation and signoff flows.
Primary responsibilities include design implementation, flow development, and PPA optimization.
Must-have technical skills and experience.
Bachelor's degree (BS) with minimum 4 years of relevant experience, or Master’s degree (MS) with minimum 2 years of relevant experience. Relevant fields include Electrical Engineering, Electronics, Computer Engineering, Physics, or related technical disciplines.
Company: Cadence Design Systems
Headquarters: San Jose, California, USA
Cadence Design Systems is a global electronic design automation company that provides software, hardware, and intellectual property for designing advanced semiconductor chips. With over 25 years in the industry, Cadence is known for its innovative technology solutions and has been recognized by Fortune Magazine as one of the 100 Best Companies to Work For. The company is dedicated to solving complex technical challenges in order to enable customers to create revolutionary products and experiences.
