Design Engineer - Memory Layout

Job Title

Design Engineer - Memory Layout

Role Summary

Member of the PHYSICAL IP – MEMORY group in Noida responsible for full‑custom memory and array layout from floorplanning through final verification. The role focuses on floor planning, metal planning and layout techniques to optimize power, performance and area (PPA) for advanced process nodes.

Experience Level

Entry-level — typically around 2+ years of relevant layout design experience.

Responsibilities

Primary duties include physical layout and verification tasks for memory IP and associated circuit blocks.

• Implement full‑custom layouts of high‑performance arrays and memory blocks from schematics through final verification and review.
• Perform floorplanning and metal planning to meet PPA targets in advanced process technologies.
• Apply and interpret physical design rules for manufacturability in advanced nodes.
• Create and verify complex memory cell layouts and peripheral circuitry.
• Execute physical verification (DRC/LVS/DFM) using Calibre or equivalent tools and resolve verification issues.
• Perform electro‑migration and IR checks to ensure reliability and integrity.
• Collaborate with circuit designers to identify layout/circuit tradeoffs and optimizations.

Requirements

Must-have technical skills and attributes.

• Proven experience with Cadence Virtuoso layout systems.
• Ability to understand and organise work from complex, hierarchical schematics.
• Knowledge of layout techniques to optimize power, speed and area for datapath, bitcell arrays, wordline drivers and control blocks.
• Experience diagnosing and fixing LVS and DRC issues using verification tools.
• Familiarity with DRC/LVS/DFM processes and verification flows (Calibre or equivalent).
• Experience with electro‑migration (EM) and IR analysis for reliability.
• Organized, detail oriented, and able to work within strict design and manufacturability guidelines.

Nice-to-have:

• Experience with design‑for‑manufacture in advanced nodes (7nm/5nm/3nm/2nm).
• Programming or scripting experience (Tcl, Perl, shell, Skill, Scheme).
• Experience identifying design tradeoffs with circuit design leads based on analysis and assumptions.

Education Requirements

Bachelor's or Master's degree (engineering or related) or equivalent practical experience; explicit degree field not specified in the posting.

About the Company

Company: Arm

Headquarters: Cambridge, United Kingdom

ARM is a global leader in semiconductor and software design, driving innovation in computing technology. The company specializes in designing processors and systems that provide the essential building blocks for electronic devices. ARM's architecture is widely used in smartphones, servers, and IoT devices, and its collaborative culture fosters bold thinking, diversity, and high-impact benefits for its talented workforce.