Design Engineer II

Job Title

Design Engineer II

Role Summary

Hands-on Design-for-Test (DFT) engineer responsible for implementing and validating on-chip test features and supporting chip tape-outs and post-silicon bring-up. Works with RTL/netlist, gate-level and timing simulations, and test insertion flows across design, synthesis, physical design, and STA teams.

Role focuses on scan/ATPG/JTAG/MBIST flows, test-structure insertion, memory BIST, ATE bring-up, and debug using industry tools and scripting.

Experience Level

Mid-level — typically 2–5 years of relevant industry experience.

Responsibilities

Key responsibilities include:

• Design and validate DFT features (scan, ATPG, JTAG, MBIST) across block and chip levels.
• Perform gate-level and timing (SDF) simulations to validate testability and fault coverage.
• Insert and verify test structures, test point insertion and coverage-improvement techniques.
• Generate, insert, and verify memory BIST at RTL and netlist levels.
• Support chip tape-outs, ATE bring-up, and post-silicon debug on tester platforms.
• Collaborate with design, synthesis, physical-design and STA teams to resolve DFT issues.
• Run block-level and chip static timing analysis (STA) flows related to test modes and timing constraints.
• Develop and maintain scripts (Perl/Tcl) to automate DFT flows and verification tasks.

Requirements

Must-have skills and experience:

• Strong practical knowledge of SCAN, ATPG, JTAG and MBIST methodologies.
• Experience with chip tape-outs including ATE bring-up and post-silicon debug.
• Experience with gate-level and timing (SDF) simulation for test verification.
• Experience with test-structure design, ATPG fault models, and test point strategies.
• Proficiency using industry-standard DFT tools for scan insertion, ATPG, MBIST and JTAG (Cadence/Tessent preferred).
• Familiarity with Analog PHY and analog macro testing and JTAG standards (IEEE 1149.1 / 1149.6).
• Practical knowledge of test mode timing constraints and running STA flows.
• Strong scripting skills (Perl/Tcl) and good communication and teamwork skills.

Education Requirements

Bachelor's or Master’s in Engineering (BE/B.Tech/ME/M.Tech) or equivalent degree in a relevant technical discipline, or equivalent practical experience. The role expects approximately 2–5 years of relevant industry experience.

About the Company

Company: Cadence Design Systems

Headquarters: San Jose, California, USA

Cadence Design Systems is a global electronic design automation company that provides software, hardware, and intellectual property for designing advanced semiconductor chips. With over 25 years in the industry, Cadence is known for its innovative technology solutions and has been recognized by Fortune Magazine as one of the 100 Best Companies to Work For. The company is dedicated to solving complex technical challenges in order to enable customers to create revolutionary products and experiences.