Design Engineer II

Job Title

Design Engineer II

Role Summary

Responsible for post-silicon characterization and validation of analog and digital IP-based silicon solutions. The role leads a small engineering team and coordinates lab-based testing, interoperability and compliance validation with R&D and marketing teams worldwide.

Experience Level

Mid-level. Posted experience guidance: 2–10 years post-silicon experience with a BTech, or ~10 years with an MTech. Requires 5–7 years of experience leading/mentoring a small team.

Responsibilities

Key responsibilities include:

• Lead and mentor a small team to plan and execute post-silicon lab tests and silicon characterization activities.
• Define test scope and coordinate with R&D and marketing to deliver results on schedule.
• Characterize analog and digital IP and validate PHY and protocol behavior for high-speed SERDES interfaces.
• Develop electrical, protocol, interoperability and compliance test suites derived from standards.
• Perform silicon debug using lab equipment (oscilloscopes, BER testers, protocol exercisers/analyzers) and run root-cause analysis.
• Develop lab automation and analysis scripts to streamline testing and failure diagnosis.
• Design and review PCBs at schematic and layout level and resolve signal and power integrity issues.
• Develop and execute reliability qualification tests (ESD, Latchup, HTOL).
• Collaborate with remote teams globally and manage multiple priorities and deliverables.

Requirements

Must-have skills and experience:

• Post-silicon PHY, systems interoperability and compliance testing experience.
• Physical and protocol layer experience on at least one high-speed SERDES (Ethernet, PCIe, CXL, UCIe).
• Strong debugging skills and hands-on experience with oscilloscopes, BER testers, protocol analyzers/exercisers.
• Ability to interpret standards and develop electrical and protocol test suites for interoperability and compliance.
• Experience developing lab automation and test-result analysis; proficient in Python and C/C++.
• Expert-level Verilog RTL for FPGA development.
• PCB schematic and layout familiarity; high-speed interface design techniques; signal and power integrity analysis and fixes.
• 5–7 years of experience leading/mentoring a small team of engineers.
• Nice-to-have: experience with PCIe/UCIe LTSSM states, UCIe interfaces, Ethernet standards and CXL.

Education Requirements

Mentions Bachelor of Technology (BTech) and Master of Technology (MTech). The posting specifies 2–10 years of experience when holding a BTech or ~10 years when holding an MTech. Equivalent practical experience is implied where appropriate.

About the Company

Company: Cadence Design Systems

Headquarters: San Jose, California, USA

Cadence Design Systems is a global electronic design automation company that provides software, hardware, and intellectual property for designing advanced semiconductor chips. With over 25 years in the industry, Cadence is known for its innovative technology solutions and has been recognized by Fortune Magazine as one of the 100 Best Companies to Work For. The company is dedicated to solving complex technical challenges in order to enable customers to create revolutionary products and experiences.