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Design Engineer II

Cadence Design Systems
September 14, 2026
Full-time
On-site
Nanjing, Jiangsu, China
RTL Design Jobs, Level - Mid-Career

Job Title

Design Engineer II

Role Summary

Frontend design engineer focused on advanced physical IP development for high-performance serial-interface PHYs. Deliver RTL, low-power features, synthesis constraints, and support verification, layout, backend, lab validation, and customer integration.

Work within a global, cross-functional team to complete IP projects from specification through pre/post-silicon support.

Experience Level

Mid-level: Design Engineer II. Typically requires 1+ years of relevant industry experience.

Responsibilities

Primary responsibilities include RTL implementation and cross-functional coordination to deliver production-quality IP.

  • Implement and refine RTL to meet feature and performance requirements for high-speed PHY IP (eUSB2v2, USB4-PHY, PCIe, ONFI, eDP/DP, SATA).
  • Develop synthesis constraints, power-management strategies, and DFT; support low-power features such as power islands and state retention.
  • Define verification coverage, test strategies, corner conditions, and stimulus; support FPGA/Palladium bring-up and validation.
  • Coordinate with project management and cross-geography teams to meet schedules and release-quality deliverables.
  • Support integration, QA, lab bring-up/validation, and provide pre/post-silicon customer support.

Requirements

Must-have skills and core expectations.

  • 1+ years of relevant industry experience in RTL or ASIC design flows.
  • Proficient with RTL design/verification best practices and end-to-end ASIC methodology.
  • Familiarity with one or more serial interface standards (USB, DP, PCIe, Ethernet, etc.).
  • Basic understanding of analog mixed-signal concepts, SI/PI, and post-silicon validation.
  • Strong cross-functional communication skills in both English and Mandarin.
  • Self-starter able to manage multiple tasks and priorities; effective working independently and in teams.

Nice-to-have:

  • Direct experience with high-speed serial link IPs in advanced technology nodes.
  • Knowledge of SystemVerilog, Python, C/C++.
  • Experience with Cadence ASIC design tools.

Education Requirements

MS or BS in Electrical Engineering, Computer Engineering, or a related technical field (as stated in the posting).


About the Company

Company: Cadence Design Systems

Headquarters: San Jose, California, USA

Cadence Design Systems is a global electronic design automation company that provides software, hardware, and intellectual property for designing advanced semiconductor chips. With over 25 years in the industry, Cadence is known for its innovative technology solutions and has been recognized by Fortune Magazine as one of the 100 Best Companies to Work For. The company is dedicated to solving complex technical challenges in order to enable customers to create revolutionary products and experiences.

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Date Posted: 2026-09-12