Design Engineer II

Job Title

Design Engineer II

Role Summary

Join a team developing high-performance physical IP for industry-standard protocols. The role focuses on digital RTL verification, building reusable verification components and environments, and driving verification closure for production-quality IP.

This position sits on a small, cross-functional IP design and verification team and requires clear technical communication with design, verification, and project management stakeholders across multiple geographies.

Experience Level

Mid-level. Typical candidate is an experienced individual contributor with several years of verification or digital design experience (not explicitly quantified in the posting).

Responsibilities

Primary responsibilities include independent verification work and contribution to verification flows and closure activities.

• Verify digital RTL and deliver high-quality verification environments and reusable components.
• Develop and execute test plans; drive functional and code coverage closure.
• Implement metric-driven verification practices and verification architecture elements.
• Create and maintain SystemVerilog assertions and functional coverage points.
• Collaborate with design, verification, physical and analog teams to coordinate project status and fixes.
• Contribute to verification flow and tooling improvements; script automation as needed.
• Work onsite in the Montreal office; travel as required (approximately 5% or less).

Requirements

Key technical and professional requirements. Education specifics are listed separately below.

• Must-have: understanding of verification architecture and methodologies, including Metric-Driven Verification and UVM concepts.
• Must-have: knowledge of SystemVerilog Assertions (SVA) and digital design flow fundamentals.
• Must-have: strong logic fundamentals, problem solving, and communication skills; ability to work independently and in a small team.
• Nice-to-have: hands-on experience coding in SystemVerilog UVM.
• Nice-to-have: scripting experience (Python, Perl, Ruby, sed, awk) for testbench and flow automation.
• Nice-to-have: exposure to standard protocols (PCIe, USB, SATA, Ethernet, DisplayPort, HDMI), formal verification, mixed-signal verification, Cadence tools, or low-power verification (CPF/UPF).

Education Requirements

Minimum: Bachelor's degree in Electrical Engineering, Computer Engineering, Computer Science, or a related technical field (B.Sc./B.Eng or equivalent). Preferred: Master's degree in EE/CPE/CS. The posting notes related technical degrees are acceptable; no specific certifications required. (Education items were removed from the Requirements section to avoid duplication.)

Compensation: The annual salary range for this location is 73,500 - 136,500 CAD (annual); actual pay will depend on experience and location. Additional incentive compensation and benefits may be available.

About the Company

Company: Cadence Design Systems

Headquarters: San Jose, California, USA

Cadence Design Systems is a global electronic design automation company that provides software, hardware, and intellectual property for designing advanced semiconductor chips. With over 25 years in the industry, Cadence is known for its innovative technology solutions and has been recognized by Fortune Magazine as one of the 100 Best Companies to Work For. The company is dedicated to solving complex technical challenges in order to enable customers to create revolutionary products and experiences.