Design Engineer I (Synthesis/LEC/CLP)
Cadence Design SystemsJob Title
Design Engineer I (Synthesis/LEC/CLP)
Role Summary
Work on synthesis, logical equivalence checking (LEC), and low-power (CLP) tasks across ASIC design blocks. The role supports execution-level verification, constraint review, and basic scripting to help move designs toward sign-off.
This position is on a small engineering team and is intended for an early-career engineer building practical EDA and ASIC-flow expertise.
Experience Level
Entry-level - 0–2 years of professional experience (internship or academic project experience with ASIC flows is acceptable).
Responsibilities
Primary day-to-day responsibilities include:
- Run and monitor LEC, logic synthesis, and Conformal low-power jobs across design blocks.
- Support and review constraints, generate constraint files, and perform basic debug.
- Track and document LEC and synthesis status, issues, and results for blocks.
- Apply power-intent basics to support CLP sign-off activities.
- Implement ECO scripts and perform basic scripting tasks using Tcl/Perl/Python.
- Maintain clear run documentation and report findings to the team.
Requirements
Must-have technical skills and attributes:
- 0–2 years of hands-on or internship/project experience with ASIC flows (preferred, not mandatory beyond readiness to learn).
- Basic understanding of the complete ASIC design flow (synthesis, verification, sign-off concepts).
- Basic scripting proficiency in Python, Perl, Tcl, or Unix shell.
- Strong analytical and problem-solving skills; willingness to learn EDA tool flows.
- Good communication and teamwork skills.
Nice-to-have:
- Exposure to Cadence tools such as Genus and Conformal through coursework or internship.
- Basic knowledge of digital logic design and computer architecture.
Education Requirements
BE/BTech/ME/MS/MTech (Bachelor's or Master’s) in Electrical or Electronics Engineering or equivalent technical degree. The posting allows equivalent practical experience; internship or academic project experience with ASIC flows is noted as relevant.
We’re doing work that matters - this role is an opportunity to develop practical EDA and ASIC design skills early in your career.
About the Company
Company: Cadence Design Systems
Headquarters: San Jose, California, USA
Cadence Design Systems is a global electronic design automation company that provides software, hardware, and intellectual property for designing advanced semiconductor chips. With over 25 years in the industry, Cadence is known for its innovative technology solutions and has been recognized by Fortune Magazine as one of the 100 Best Companies to Work For. The company is dedicated to solving complex technical challenges in order to enable customers to create revolutionary products and experiences.
