Design Engineer I (Post-Silicon Electrical Validation Engineer)
Full-time on-site role in the Cadence IP group responsible for validating the electrical performance of internal silicon test chips, debugging silicon issues, and producing high-quality characterization reports. The engineer will work closely with analog and digital design teams and other cross-functional groups to ensure silicon reliability and functionality.
Work includes electrical characterization of high-speed SERDES designs and other IP used in modern communications and compute systems.
Entry-level — 0–2 years of relevant work experience.
Primary responsibilities include planning and executing electrical validation, debugging, and reporting:
Must-have technical skills and attributes; education expectations are summarized separately below.
Bachelor's or Master’s degree in Electrical Engineering is specified; candidates with equivalent practical experience are also considered. The role is open to applicants with 0–2 years of relevant work experience.
California annual salary range: $88,900 to $165,100; incentive compensation (bonus, equity) and benefits may also apply.
Company: Cadence Design Systems
Headquarters: San Jose, California, USA
Cadence Design Systems is a global electronic design automation company that provides software, hardware, and intellectual property for designing advanced semiconductor chips. With over 25 years in the industry, Cadence is known for its innovative technology solutions and has been recognized by Fortune Magazine as one of the 100 Best Companies to Work For. The company is dedicated to solving complex technical challenges in order to enable customers to create revolutionary products and experiences.
