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Design Engineer I

Cadence Design Systems
September 01, 2026
Full-time
On-site
Cary, North Carolina, United States
$88,900 - $165,100 USD yearly
DFT Jobs, Level - Entry or Early Career

Job Title

Design Engineer I

Role Summary

Design and implement SoC-level DFT architecture and flows for large, complex ASIC designs within the Palladium platform group. The role spans architecture definition, pre-silicon implementation and sign-off, and post-silicon debug and yield analysis.

Experience Level

Entry-level (Engineer I). The posting requests at least 3 years of hands-on SoC DFT experience.

Responsibilities

Primary responsibilities include:

  • Define and implement SoC-level DFT architecture for large, complex designs.
  • Develop, integrate, and support SCAN, ATPG, MBIST, BSCAN and iJTAG flows.
  • Perform DFT insertion, verification, and coverage analysis at block and SoC levels.
  • Drive pre-silicon DFT sign-off, including DRC closure and coverage targets.
  • Support post-silicon debug, failure analysis and yield learning.
  • Collaborate with RTL, verification, physical design and operations teams.

Requirements

Must-have and nice-to-have skills:

Must-have:

  • At least 3 years of hands-on SoC DFT experience.
  • Strong expertise in SCAN, ATPG and MBIST.
  • Experience with pre-silicon validation and post-silicon debug.
  • Strong problem solving and debugging skills.
  • Ability to work effectively in cross-functional engineering teams.

Nice-to-have:

  • Scripting for flow automation and analysis (TCL, Perl, Python or equivalent).
  • Experience with IP-level DFT integration and reuse.
  • Exposure to low-power DFT considerations and complex clocking architectures.
  • Familiarity with manufacturing test flows and silicon yield improvement.

Education Requirements

BS degree specified in the posting; field of study not specified.

Compensation note: the posting lists a California annual range of $88,900 to $165,100; additional incentive compensation (bonus, equity) and benefits may apply.

Work on challenging SoC DFT problems with cross-functional teams.


About the Company

Company: Cadence Design Systems

Headquarters: San Jose, California, USA

Cadence Design Systems is a global electronic design automation company that provides software, hardware, and intellectual property for designing advanced semiconductor chips. With over 25 years in the industry, Cadence is known for its innovative technology solutions and has been recognized by Fortune Magazine as one of the 100 Best Companies to Work For. The company is dedicated to solving complex technical challenges in order to enable customers to create revolutionary products and experiences.

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Date Posted: 2026-08-31