Design Engineer 3 (Integration)

Job Title

Design Engineer 3 (Integration)

Role Summary

The Integration Design Engineer will be a member of the Silicon Integration Team responsible for integrating IP blocks and sectors to produce full-chip deliverables. The role covers generation of logical floorplans, full-chip behavioral models, synthesized netlists, and schematics, and requires collaboration with Architecture, Software, IP design, verification, and physical design teams.

This role is based in Manila and requires proof of the right to work in the Philippines.

Experience Level

Mid-level - typically requires at least 5 years of professional experience in custom and digital design implementation.

Responsibilities

Key responsibilities include full-chip integration tasks, design implementation, and validation activities required for tapeout.

• Integrate multiple IPs to build full-chip logical floorplans and behavioral models aligned with software and verification requirements.
• Deliver full-chip synthesized netlists, schematics, and collateral to cross-functional teams.
• Design and implement density-specific IPs and sectors (custom and digital) such as clock networks for full-chip integration.
• Perform elaboration/compilation, synthesis, equivalence checks, DFT steps, timing closure (SPICE and/or STA), and power/performance analysis.
• Run full-chip tapeout-gating audits: EM/IR analysis, NetERC, PDN extraction, SSO simulations, and ESD checks.
• Work with functional teams to debug and resolve integration, timing, power, and electrical issues.

Requirements

Concise list of required and preferred skills and experience.

• Must-have: Minimum ~5 years experience in custom and digital design implementation; strong expertise in Verilog and SystemVerilog.
• Must-have: Practical knowledge of custom design flow and transistor-level semiconductor principles; experience with schematic/layout tools (e.g., Cadence Virtuoso) and SPICE-based characterization and power/performance simulation.
• Must-have: Digital design flow experience: RTL coding and verification, linting, elaboration/compilation, synthesis, equivalence checking, SDC, and STA using industry tools.
• Must-have: Scripting/coding skills (Perl, Tcl, shell, Skill, Python).
• Nice-to-have: Experience with FPGA/CPLD design and integration; IP and full-chip functional verification exposure.
• Nice-to-have: Familiarity with DFT flow and ATPG generation; experience with tools such as Xcelium, Genus, Innovus, Tempus, or Tempus-equivalent flows.
• Nice-to-have: Project leadership or product development cycle experience (planning, resourcing, tapeout, silicon characterization/validation).

Education Requirements

Bachelor's or Master's degree in Electronics, Computer, or Electrical Engineering (BS/MS in Electronics/Computer/Electrical Engineering) is specified.

About the Company

Company: Lattice Semiconductor

Headquarters: Portland, Oregon, USA

Lattice Semiconductor specializes in low power, small-form-factor programmable logic devices and solutions. The company is known for its innovative technology that enables a wide range of applications, including communication, consumer, and industrial markets.