Design Architect

Job Title

Design Architect

Role Summary

Join the Cadence HSV group to design and verify representative SoC sub-systems for Palladium and Protium emulation platforms. The role focuses on building ARM CSS-based systems using Cadence AVIPs and IP, porting them to emulator hardware/software, and improving functional correctness and performance.

Work involves RTL and verification components (SystemVerilog/Verilog, SV-UVM), C/C++ software, and development of system-level RTL methodologies and automation tools.

Experience Level

Senior - 15–18 years of hands-on hardware RTL development and verification experience; experience with emulation and SoC performance analysis required.

Responsibilities

Key responsibilities include:

• Lead design and integration of representative SoC sub-systems using partner systems (ARM) and Cadence AVIPs/IP.
• Implement and verify SystemVerilog/Verilog components and software components in C/C++, and develop SV-UVM testbenches.
• Port designs to Palladium and Protium emulator hardware/software and validate functional correctness.
• Develop and maintain system-level RTL methodologies for scalable, reusable SoC integration.
• Measure and analyze performance of AVIPs, compiler interaction, and emulator hardware; recommend and implement performance improvements.
• Collaborate with cross-functional teams and external partners to resolve complex integration and verification issues.
• Document architectures, designs, and verification strategies; mentor and guide other engineers.

Requirements

Must-have and preferred qualifications:

• Must-have: 15–18 years of hands-on HW RTL development and verification experience.
• Must-have: Emulation experience on Cadence Palladium and/or Protium platforms.
• Must-have: Expertise in AMBA and CHI protocols and experience with ARM bus protocols.
• Must-have: Experience with SoC design and integration and performance analysis of complex hardware-software systems.
• Must-have: Strong problem-solving skills, good communication, and ability to propose solutions to complex issues.
• Nice-to-have: Familiarity or interest in developing SoC integration and verification automation; experience with SV-UVM.
• Nice-to-have: Familiarity with PCIe, CXL, or tools that leverage AI/ML techniques.

Education Requirements

Not specified.

About the Company

Company: Cadence Design Systems

Headquarters: San Jose, California, USA

Cadence Design Systems is a global electronic design automation company that provides software, hardware, and intellectual property for designing advanced semiconductor chips. With over 25 years in the industry, Cadence is known for its innovative technology solutions and has been recognized by Fortune Magazine as one of the 100 Best Companies to Work For. The company is dedicated to solving complex technical challenges in order to enable customers to create revolutionary products and experiences.