Debug/Trace/Profiling Design Engineer
SiFiveJob Title
Debug/Trace/Profiling Design Engineer
Role Summary
Design and deliver debug, trace, and profiling hardware IP for RISC-V-based SoCs. Work on configurable RTL generators, integrate with SiFive's Chisel/FIRRTL framework, and collaborate with architecture, software, verification and customer teams to ship high-quality IP.
Small team environment focused on fast hardware delivery, configurability, and tooling/verification integration.
Experience Level
Senior — 7+ years of industry experience in architecture, microarchitecture and RTL design for debug/trace/profiling hardware.
Responsibilities
Deliver and maintain debug/trace/profiling IP and support its integration and verification across product lines.
- Architect, design, and implement debug, trace and profiling hardware.
- Collaborate with architecture, performance, software and hardware teams on specifications and microarchitecture exploration.
- Implement RTL generators that self-configure to support extensive configurability.
- Integrate designs into the Chisel/FIRRTL framework and contribute framework improvements for generation of documentation, tests, and verification harnesses.
- Create and execute verification plans; perform sandbox verification and hand off to verification teams.
- Produce and maintain design documentation and participate in cross-team knowledge sharing.
Requirements
Key qualifications for candidates. Must-have items are listed first; nice-to-have items follow.
Must-have
- Deep knowledge of debug, trace and profiling architectures and concepts.
- Experience with debug interfaces (JTAG, cJTAG) and debugging/profiling tools and methods.
- Strong understanding of CPU architectures, power management and SoC design.
- Proficiency in RTL design (Verilog, SystemVerilog, or VHDL).
- Experience leading and directly contributing to architecture, microarchitecture and RTL design for debug/trace/profiling hardware for high-performance processors (7+ years).
- Ability to work collaboratively; strong attention to detail and quality-focused engineering practices.
- Familiarity with at least one object-oriented and/or functional programming language.
Nice-to-have
- Experience with Chisel/Scala and the RISC-V ecosystem.
- Familiarity with Git, Jira, Confluence and hardware verification tooling.
Education Requirements
MS or PhD in Electrical Engineering, Computer Engineering, Computer Science, or a related technical discipline.
About the Company
Company: SiFive
Headquarters: San Mateo, California, United States
SiFive is a pioneering company in the RISC-V ecosystem, focused on transforming the future of computing by delivering high-performance, data-intensive RISC-V solutions. Their compute platforms empower leading technology firms to innovate across various markets, including AI, machine learning, and automotive sectors. SiFive is recognized for its commitment to ongoing innovation and fostering collaboration among talented teams, impacting lives by enabling advanced chip design.
