DDR PHY Senior Lead Digital Design Engineer

Job Title

DDR PHY Senior Lead Digital Design Engineer

Role Summary

Design and lead development of digital components for high-performance DDR/LPDDR PHY memory interface IP. Work across architecture, RTL implementation, synthesis, DFT, verification support, and silicon bring-up within an ASIC/SoC engineering team.

Experience Level

Senior / Lead - typically requires 5+ years of experience in digital design and front-end implementation of complex ASIC/SoC/IP designs.

Responsibilities

Main responsibilities include design, implementation, verification support, and delivery of DDR PHY digital IP.

• Architect and implement digital RTL for DDR/LPDDR PHY interfaces.
• Define micro-architecture, perform RTL coding, integration and debug of complex IP.
• Ensure RTL quality: lint, CDC/RDC checks, reset handling, and design rule checks.
• Collaborate with verification to develop plans, close coverage gaps, and debug issues.
• Develop synthesis/timing constraints, analyze timing reports, and deliver timing-clean netlists.
• Create and maintain UPF low-power intent and perform low-power equivalence and signoff checks.
• Implement and validate DFT (scan insertion, ATPG) and optimize fault coverage.
• Support pre-silicon and post-silicon bring-up, characterization, and issue resolution.
• Work with physical design, STA, verification, DFT, firmware, and SoC integration teams to meet milestones.

Requirements

Key must-have skills and experience for this role, followed by preferred skills.

• Must have: 5+ years experience in digital design and front-end implementation of complex ASIC/SoC/IP designs.
• Must have: Strong RTL development skills in Verilog/SystemVerilog and solid micro-architecture understanding.
• Must have: Practical experience with front-end flows: lint, CDC/RDC, low-power verification, synthesis, static timing analysis (STA), and DFT.
• Must have: Familiarity with industry-standard EDA tools for RTL design, verification, synthesis, and timing closure.
• Must have: Strong debugging, problem-solving, communication, and collaboration skills working with global teams.

• Nice to have: Previous work on DDR/LPDDR PHY, high-speed interface, or mixed-signal IP.
• Nice to have: Knowledge of UPF and power-aware design methodologies.
• Nice to have: Hands-on experience with scan insertion, ATPG, silicon debug, and post-silicon validation/characterization.
• Nice to have: Experience driving methodology improvements and automation in the design flow.

Education Requirements

Posting specifies technical degrees: B.Tech/Bachelor's, M.Tech/Master's, or PhD in Electrical Engineering, Electronics Engineering, Computer Engineering, Computer Science, or related technical disciplines. The posting includes degree-to-experience mappings: Bachelor's +3 years, Master's +2 years, or PhD +1 year for related ASIC design/verification/validation experience.

About the Company

Company: Qualcomm

Headquarters: San Diego, California, United States

Qualcomm is a global leader in semiconductor and telecommunications equipment, specializing in mobile technologies and innovations. Known for its Adreno GPUs, the company provides solutions enabling advancements in mobile gaming, AI, VR/AR, and autonomous driving. Qualcomm's cutting-edge technology and commitment to high-performance, power-efficient designs drive the evolution of mobile graphics and connectivity worldwide.