DDR/LPDDR IP Design Principal Engineer

Job Title

DDR/LPDDR IP Design Principal Engineer

Role Summary

Principal-level engineer responsible for architecture, RTL design, verification, and delivery of DDR/LPDDR memory IP for ASIC/SoC products. The role sits in the ASIC Digital Design / Hardware Engineering organization based in Wuhan, Hubei, China and works closely with system, PHY, and verification teams to deliver production-ready IP.

Experience Level

Senior (Principal) - expected to be an experienced engineer; typically a candidate with senior/principal-level experience in memory IP or ASIC digital design (guidance: 7+ years).

Responsibilities

Core responsibilities for this principal engineer role include:

• Lead architecture and micro-architecture for DDR/LPDDR controller and PHY IP.
• Develop and review RTL (implementation and coding standards) and deliver synthesizable designs.
• Define and execute verification plans using industry methodologies to ensure functional and timing correctness.
• Perform timing closure support, timing margin analysis, and collaborate with physical design teams.
• Drive JEDEC compliance, interoperability testing, and performance characterization.
• Support IP integration into customer SoCs and resolve silicon bring-up issues.
• Mentor and guide other engineers, and coordinate cross-functional engineering activities.

Requirements

Key must-have and desirable qualifications for candidates:

• Must-have: Proven experience designing and delivering DDR/LPDDR memory controller and/or PHY IP for ASIC/SoC products.
• Must-have: Strong RTL skills (SystemVerilog or Verilog) and experience with verification methodologies and testbenches (e.g., UVM).
• Must-have: Experience with timing analysis, timing closure, and working with place-and-route/physical design teams.
• Must-have: Practical experience with JEDEC memory standards, signal integrity considerations, and silicon bring-up troubleshooting.
• Nice-to-have: Experience with PHY analog/PHY integration, PHY validation, or customer-facing IP support.
• Nice-to-have: Prior experience in a principal or lead engineering role, and experience mentoring junior engineers.

Education Requirements

Not specified.

About the Company

Company: Synopsys

Headquarters: Mountain View, California, USA

Synopsys is a leading company in electronic design automation (EDA) and semiconductor IP solutions. It provides tools and services for designing and verifying complex semiconductor devices and systems. The company plays a pivotal role in the semiconductor industry, helping engineers innovate and deliver higher-quality products faster. Synopsys is committed to advancing technology standards and offers a range of software and hardware solutions to its clients globally.