Job Title
Data Fabric Verification Engineer (SystemVerilog & Formal)
Role Summary
Perform functional verification of data fabric and related RTL using SystemVerilog and formal methods. Design verification environments, develop test sequences, and work with RTL designers to ensure verification completeness and quality.
Long-term, full-time on-site role based in Sunnyvale, CA.
Experience Level
Mid-level β typically requires at least 5 years of relevant verification experience.
Responsibilities
Key duties include:
- Design and implement SystemVerilog testbenches and verification environments.
- Write and maintain directed and constrained-random test sequences and regression suites.
- Apply formal verification tools and assertion-based techniques to validate RTL.
- Collaborate with RTL designers to reproduce, debug, and resolve functional issues.
- Track verification quality metrics, report coverage, and drive closure.
Requirements
Must-have skills and experience:
- Strong expertise in SystemVerilog and verification environment development.
- Practical experience with formal verification tools and methodologies.
- Solid understanding of RTL design and ability to debug RTL/verification interactions.
- Experience writing test sequences and building regression suites.
- Minimum of approximately 5 years in ASIC/SoC functional verification or equivalent.
- Ability to coordinate with engineering teams and report verification metrics.
Nice-to-have:
- Experience verifying data fabric, interconnects, or similar on-chip communication fabrics.
Education Requirements
Preferred: Bachelor's or Master's degree in Computer Engineering, Electrical Engineering, Computer Science, or a closely related technical field.
About the Company
Company: iFlow
Headquarters: Sunnyvale, CA, United States
iFlow is a technology company focused on hardware and data fabric design and verification, hiring engineers skilled in SystemVerilog, RTL design, and formal verification methodologies.

Date Posted: 2026-07-28