Data Center SoC Power & Limits Architect

Job Title

Data Center SoC Power & Limits Architect

Role Summary

The Data Center SoC Power & Limits Architect defines and drives end-to-end power, thermal, and system limits architecture for large-scale compute platforms (SoC, server, rack, cluster) to enable sustained performance within constrained power, cooling, and reliability envelopes.

This role partners with silicon, platform, firmware/software, and data-center teams to architect power budgeting, dynamic control, telemetry, and limit-enforcement mechanisms across hardware and software layers.

Experience Level

Senior — typically requires 10+ years of experience in power architecture, system architecture, or related domains; senior-level technical leadership and cross-functional collaboration expected.

Responsibilities

Primary responsibilities include architecting power and limits systems across layers and validating designs via modeling and workload analysis.

• Define holistic power, thermal, and electrical limits across silicon, board, system, rack, and cluster levels.
• Architect power budgeting, allocation, and enforcement mechanisms for CPU, GPU, memory, accelerators, and I/O.
• Design dynamic power control and closed-loop limit-management systems (e.g., DVFS/DCVS, fast transient control, power capping, thermal throttling).
• Specify telemetry and interface requirements for sensors, BMC/EC, firmware, and system software to enable real-time monitoring and decision making.
• Collaborate across silicon, platform, firmware/software, and data-center infrastructure teams to define hardware/software partitioning for limits enforcement.
• Develop system-level models and simulators and perform workload-driven analysis to validate architecture trade-offs and predict performance vs. constraints.
• Drive innovations in power delivery efficiency, thermal-aware scheduling, and rack/cluster-level power orchestration.

Requirements

Must-have technical skills and experience; education and formal degree requirements are listed under Education Requirements below.

• Deep expertise in power management systems, limits control, and thermal/electrical constraints for high-performance systems.
• Practical experience with DVFS/DCVS, power capping, closed-loop control systems, and limit management.
• Strong understanding of data-center/server architecture (CPU/GPU/accelerators, memory) and power delivery networks (VRs, PDN, rack power distribution).
• Experience defining telemetry, sensors, and system monitoring interfaces; integration with platform controllers and orchestration layers.
• Experience with system-level modeling and analysis tools (MATLAB/Simulink, architectural simulators, Python) and workload-driven validation.
• Proven ability to collaborate across hardware and software teams and to translate architecture into implementable requirements.

Education Requirements

One of the following is required: Bachelor's degree in Science, Engineering, or related field plus 6+ years of ASIC design/verification/validation/integration or related experience; or Master's degree in Science, Engineering, or related field plus 5+ years of such experience; or PhD in Science, Engineering, or related field plus 4+ years of such experience.

About the Company

Company: Qualcomm

Headquarters: San Diego, California, United States

Qualcomm is a global leader in semiconductor and telecommunications equipment, specializing in mobile technologies and innovations. Known for its Adreno GPUs, the company provides solutions enabling advancements in mobile gaming, AI, VR/AR, and autonomous driving. Qualcomm's cutting-edge technology and commitment to high-performance, power-efficient designs drive the evolution of mobile graphics and connectivity worldwide.