CST Application Engineer Intern - Silicon

Job Title

CST Application Engineer Intern - Silicon

Role Summary

This is a three-month, summer 2027 cohort internship on the Cadence Customer Success Team (CST) in San Jose. The intern will receive hands-on training and work with application engineers to support silicon and systems design workflows using Cadence EDA tools.

Experience Level

Entry-level internship. Targeted at rising seniors and undergraduate students in STEM programs seeking a summer internship.

Responsibilities

Work as part of a cohort to learn and apply EDA workflows; assist application engineers and technical staff on customer-facing and internal projects.

• Participate in structured training and hands-on labs covering system/package design, digital and analog IC design and simulation, verification, and physical implementation.
• Support application engineers by running simulations, executing design flows, and assisting with signoff analyses (timing, IR drop, power, signal integrity).
• Contribute to embedded software and hardware/software co-verification tasks and basic hardware emulation activities.
• Use UNIX, C/C++, and scripting languages (Python, Tcl, Perl) to automate, debug, and document flows.
• Document results, present findings to peers and mentors, and communicate technical status clearly.

Requirements

Essential attributes and preferred technical experience for successful candidates.

• Must-have: Ability to manage multiple complex assignments and strong communication, presentation, analytical, and problem-solving skills.
• Must-have: Availability to work full time for the three-month summer 2027 internship in San Jose.
• Preferred: Experience or familiarity with electronic design automation (EDA) tools and foundational silicon, package, or board design concepts.
• Preferred: Exposure to AI applications in design flows and methodologies.
• Preferred: Practical experience with UNIX, C/C++, Python, Tcl, or Perl and familiarity with digital/analog physical design, verification, or signoff analysis.

Education Requirements

Must be currently enrolled in an accredited undergraduate STEM program. The posting targets rising seniors pursuing a bachelors degree in electrical engineering, computer engineering, or another STEM discipline.

About the Company

Company: Cadence Design Systems

Headquarters: San Jose, California, USA

Cadence Design Systems is a global electronic design automation company that provides software, hardware, and intellectual property for designing advanced semiconductor chips. With over 25 years in the industry, Cadence is known for its innovative technology solutions and has been recognized by Fortune Magazine as one of the 100 Best Companies to Work For. The company is dedicated to solving complex technical challenges in order to enable customers to create revolutionary products and experiences.