CPU STA/Timing Engineer (Lead/Staff/Senior Staff)

Job Title

CPU STA/Timing Engineer (Lead/Staff/Senior Staff)

Role Summary

Lead timing analysis and closure for high-performance CPU core and uncore designs. Work with CPU microarchitecture, RTL, physical design, DFT and CAD teams to define timing constraints, perform static timing analysis (STA), and deliver signoff-quality timing for block, cluster, and full‑chip hierarchies.

Experience Level

Senior. Minimum qualifications in the posting: Bachelor's + 2+ years hardware engineering experience, Master's + 1+ year, or PhD. Preferred: MS with 3+ years of hands-on STA and timing-closure experience.

Responsibilities

Primary responsibilities include timing analysis, cross-team collaboration, and enabling CPU frequency closure.

• Perform STA for high-performance CPU designs at block, cluster, and SoC/top-level hierarchies across multiple modes, corners, and scenarios.
• Work with CPU microarchitecture, RTL, and DFT teams to define, implement, and validate timing constraints aligned to performance goals.
• Analyze frequency-critical CPU paths (core, cache, interconnect, clocking) and drive logic or micro-architectural fixes with RTL teams.
• Provide actionable timing feedback to physical design engineers to enable CPU frequency and timing closure.
• Develop and improve CPU-specific timing flows and infrastructure in partnership with CAD and methodology teams.
• Generate and review timing ECOs (logic and physical) to close setup, hold, noise, and cross-talk violations.
• Contribute to CPU timing methodology, best practices, and documentation for consistent signoff quality.

Requirements

Must-have technical skills and experience (education items summarized separately under Education Requirements).

• Proven experience with STA and timing-closure for high-performance CPU or processor-class SoCs.
• Expertise in multi-clock, multi-domain CPU designs and frequency-critical path analysis.
• Hands-on knowledge of timing ECO techniques and implementation for frequency closure.
• Solid understanding of standard cell libraries, CPU-critical path optimization, and timing trade-offs.
• Familiarity with timing effects (noise, cross-talk, OCV/variation) and worst-case corner selection for timing signoff.
• Working knowledge of synthesis, place & route, and tape-out flows.
• Working knowledge of HDL languages such as Verilog and basic CPU/SoC architecture concepts.
• Strong communication skills to coordinate with architects, RTL designers, physical design, and CAD teams.
• Preferred: experience with deep sub-micron nodes and signoff-quality closure on large CPU/SoC designs.

Education Requirements

Bachelor's degree in Computer Science, Electrical/Electronics Engineering, Engineering, or a related field plus 2+ years of hardware engineering or related experience; OR Master's degree in those fields plus 1+ year of hardware engineering or related experience; OR PhD in those fields. Preferred: MS in Electrical Engineering with 3+ years of hands-on STA and timing-closure experience. Fields referenced: Computer Science, Electrical/Electronics Engineering, Engineering, or related technical fields.

About the Company

Company: Qualcomm

Headquarters: San Diego, California, United States

Qualcomm is a global leader in semiconductor and telecommunications equipment, specializing in mobile technologies and innovations. Known for its Adreno GPUs, the company provides solutions enabling advancements in mobile gaming, AI, VR/AR, and autonomous driving. Qualcomm's cutting-edge technology and commitment to high-performance, power-efficient designs drive the evolution of mobile graphics and connectivity worldwide.