CPU STA Engineer, Sr Lead
QualcommJob Title
CPU STA Engineer, Sr Lead
Role Summary
Senior STA engineer responsible for static timing analysis and timing closure of high-speed CPU ASIC designs. Works within the hardware/physical design team on timing signoff, constraint development, power-aware timing, and implementation optimization across the ASIC flow.
Experience Level
Senior-level. The posting specifies minimum experience that varies by degree (examples: Bachelor's +3 years, Master's +2 years, PhD +1 year); the role is targeted at experienced engineers in lead or senior staff roles and commonly expects multiple years of ASIC/physical design experience.
Responsibilities
Primary responsibilities focus on STA, timing closure, and supporting physical implementation of CPU designs.
- Perform static timing analysis and timing signoff using PrimeTime and/or Tempus.
- Generate, validate, and manage constraints for complex CPU designs.
- Support place & route flow (FC/Innovus) and optimize for power, performance, and area.
- Implement and verify multi-power-domain designs with UPF/CPF definitions.
- Apply clock tree implementation techniques for high-speed designs and resolve critical paths.
- Work with formal verification tools (e.g., Formality, Conformal) as needed to support signoff.
- Troubleshoot ASIC integration and timing issues; collaborate with RTL, physical design, and CAD teams.
Requirements
Must-have technical skills and experience for successful performance in this role.
- Extensive experience in Place & Route using FC or Innovus (absolute must).
- Hands-on STA experience with PrimeTime and/or Tempus.
- Strong expertise in constraint generation and validation; experience with constraint management tools.
- Experience implementing multiple power domains and working with UPF/CPF for power intent.
- Familiarity with formal verification tools (Formality, Conformal).
- Proficiency in scripting/programming: Perl, Tcl, Python, and C++.
- Practical knowledge of CPU micro-architecture timing and critical-path analysis.
- Proven ASIC development, debugging, and low-power implementation experience.
- Verilog coding experience relevant to timing and implementation flows.
- Strong problem-solving skills and ability to drive timing closure on complex designs.
Education Requirements
Posting specifies degree-based minimums: Bachelor's, Master's, or PhD in Computer Science, Electrical/Electronics Engineering, Engineering, or a related field. It allows equivalent work experience in lieu of a degree (e.g., Bachelor's +3 years, Master's +2 years, PhD +1 year).
About the Company
Company: Qualcomm
Headquarters: San Diego, California, United States
Qualcomm is a global leader in semiconductor and telecommunications equipment, specializing in mobile technologies and innovations. Known for its Adreno GPUs, the company provides solutions enabling advancements in mobile gaming, AI, VR/AR, and autonomous driving. Qualcomm's cutting-edge technology and commitment to high-performance, power-efficient designs drive the evolution of mobile graphics and connectivity worldwide.
