CPU STA Engineer — Senior / Lead / Staff
QualcommJob Title
CPU STA Engineer — Senior / Lead / Staff
Role Summary
Perform static timing analysis (STA) and timing signoff for high-speed CPU implementations within the ASIC/SoC flow. Partner with physical design, verification and microarchitecture teams to meet timing, power and area targets for CPU blocks.
Experience Level
Senior level (Senior / Lead / Staff). The posting lists varying minimums by degree; expect multiple years of hands-on ASIC/hardware engineering experience focused on STA and physical implementation.
Responsibilities
Primary responsibilities include:
- Perform STA and timing signoff for CPU designs using PrimeTime and/or Tempus.
- Generate, validate and manage timing constraints; drive timing closure activities.
- Work with place & route and physical design teams (Fusion Compiler / Innovus) to resolve timing and PPA issues.
- Design and verify clock-tree implementation techniques for high-speed designs.
- Implement and verify multi-power-domain solutions using UPF/CPF and support low-power optimizations.
- Debug critical timing paths in collaboration with RTL, verification and lab teams.
- Support formal verification flows and review/advise on Verilog and constraint quality.
Requirements
Technical must-haves and preferred skills (education summarized below in Education Requirements):
- Must-have: Hands-on STA experience with Synopsys PrimeTime and/or Cadence Tempus.
- Must-have: Strong place & route experience with Fusion Compiler (FC) or Cadence Innovus.
- Must-have: Proven ability in constraint generation, validation and timing closure for CPU designs.
- Must-have: Experience implementing multiple power domains and working with UPF/CPF.
- Must-have: Scripting/programming skills: Perl/Tcl and Python; C++ experience expected.
- Must-have: Familiarity with Formal tools such as Formality or Conformal; Verilog coding exposure.
- Nice-to-have: Deep knowledge of CPU micro-architecture critical paths, low-power implementation techniques, and full ASIC flow for PPA optimization.
- Nice-to-have: Experience with constraint management tools and complex power/domain partitioning.
Education Requirements
Bachelor's, Master's or PhD in Computer Science, Electrical/Electronics Engineering, Engineering, or a related technical field. The posting lists varying minimum experience by degree (examples in the posting): Bachelor's typically 3–15 years or 6+ years; Master's typically 3–15 years or 5+ years; PhD typically 4+ years.
About the Company
Company: Qualcomm
Headquarters: San Diego, California, United States
Qualcomm is a global leader in semiconductor and telecommunications equipment, specializing in mobile technologies and innovations. Known for its Adreno GPUs, the company provides solutions enabling advancements in mobile gaming, AI, VR/AR, and autonomous driving. Qualcomm's cutting-edge technology and commitment to high-performance, power-efficient designs drive the evolution of mobile graphics and connectivity worldwide.
