CPU STA Engineer, Senior Engineer

Job Title

CPU STA Engineer, Senior Engineer

Role Summary

Work on static timing analysis (STA) and timing closure for high-speed CPU implementations within Qualcomm's hardware/ASIC engineering team in Hyderabad. The role focuses on timing sign-off, constraint management, power-domain timing, and collaboration with place-and-route, RTL, and verification teams to deliver production silicon.

Experience Level

Senior. The posting lists minimum academic/experience alternatives (Bachelor's +2 years, Master's +1 year, or PhD); the role expects experienced engineers with demonstrated STA and CPU implementation skills.

Responsibilities

Primary responsibilities involve STA, timing closure, and support across the ASIC implementation flow.

• Perform static timing analysis using PrimeTime and/or Tempus and drive timing sign-off.
• Generate, validate, and maintain timing constraints and manage constraint updates across teams.
• Support and optimize CPU microarchitecture critical paths for high-speed designs.
• Implement and validate multi-power-domain timing using UPF/CPF and coordinate with P&R teams.
• Work with place-and-route engineers (FC/Innovus) on timing-driven implementation and optimizations.
• Contribute to clock-tree implementation techniques and timing-driven low-power optimizations.
• Debug timing issues, coordinate with formal and functional verification groups, and support silicon bring-up.
• Automate flows and analyses using scripting where appropriate and hand off deliverables to cross-functional teams.

Requirements

Technical must-haves and desired skills. Degree requirements are summarized separately below.

• Must-have: Extensive Place & Route experience with Fusion Compiler (FC) or Innovus.
• Must-have: Proven STA experience with PrimeTime and/or Tempus.
• Must-have: Strong constraint generation and validation skills; experience with constraint-management tools.
• Must-have: Experience implementing multiple power domains and complex UPF/CPF flows.
• Must-have: Familiarity with clock-tree implementation techniques for high-speed designs and low-power implementation techniques.
• Must-have: Programming/scripting skills (Perl/Tcl, Python, C++); Verilog exposure.
• Must-have: Strong ASIC development, timing debug, and problem-solving skills focused on CPU designs.
• Nice-to-have: Formal verification tool experience (Formality/Conformal) and prior work on high-speed CPU implementations.

Education Requirements

Bachelor's degree in Computer Science, Electrical/Electronics Engineering, Engineering, or a related field with 2+ years of hardware engineering experience; OR Master's degree in those fields with 1+ year of hardware engineering experience; OR PhD in those fields. (These degree/experience alternatives are specified in the posting.)

About the Company

Company: Qualcomm

Headquarters: San Diego, California, United States

Qualcomm is a global leader in semiconductor and telecommunications equipment, specializing in mobile technologies and innovations. Known for its Adreno GPUs, the company provides solutions enabling advancements in mobile gaming, AI, VR/AR, and autonomous driving. Qualcomm's cutting-edge technology and commitment to high-performance, power-efficient designs drive the evolution of mobile graphics and connectivity worldwide.