CPU SRAM Design & Layout Engineer

Job Title

CPU SRAM Design & Layout Engineer

Role Summary

Join the High Performance CPU team to design, implement, verify, and deliver custom high-performance SRAMs and register files. The role spans schematic-level circuit design through physical layout, verification, characterization, and model generation.

The engineer will collaborate with circuit design, CAD, and physical design teams to optimize memory PPA (power, performance, area), reliability, and manufacturability.

Experience Level

Mid-level. Typical experience expectations range roughly from 2 to 5+ years depending on role scope and prior responsibilities.

Responsibilities

Primary responsibilities include ownership of memory design and physical implementation.

• Design and develop custom SRAMs and register files optimized for high performance and low power.
• Create schematics and perform circuit-level design and optimization.
• Develop memory floorplans and implement custom layouts to meet project requirements.
• Own memory implementation from architecture and floorplanning through physical verification and signoff.
• Execute and analyze LVS, DRC, ERC, and other physical verification checks.
• Perform functional verification, simulation, margin analysis, and Monte Carlo studies across PVT corners.
• Perform timing, power, and electrical characterization and generate deliverable models.
• Collaborate with CAD and Physical Design teams to resolve PPA and manufacturability issues.
• Develop and improve automation, characterization flows, and memory analysis methodologies.
• Provide layout guidance, resolve implementation issues, and drive projects to completion on schedule.

Requirements

Key technical must-haves and useful preferred skills.

• Must-have: Experience designing custom SRAM circuits and register files.
• Must-have: Experience with custom memory layout design and deep sub-micron layout implementation.
• Must-have: Proficiency with circuit simulation, Monte Carlo analysis, and static timing analysis.
• Must-have: Familiarity with layout floorplanning, hierarchical assembly, and physical verification methodologies.
• Must-have: Experience with Cadence Virtuoso and Calibre LVS/DRC verification flows.
• Must-have: Knowledge of advanced semiconductor technologies and FinFET/nanosheet process considerations.
• Nice-to-have: Experience with variation-aware simulation, memory logical models (Verilog), BIST/DFT, and complete memory development flows.
• Nice-to-have: Experience with EMIR analysis and tools such as NanoTime, Ansys EMIR, ESP-CV, Liberate.
• Nice-to-have: Automation and scripting experience (e.g., SKILL) for layout and design productivity.
• Nice-to-have: Strong understanding of semiconductor device physics, reliability, and low-power circuit techniques.

Education Requirements

Qualifications reference a Bachelor's, Master's, or PhD in Electrical Engineering, Computer Engineering, Computer Science, or a related technical field. Experience expectations vary by degree (examples in source text include multi-year experience requirements tied to degree level). "Related field" language is used; specific certifications are not specified.

About the Company

Company: Qualcomm

Headquarters: San Diego, California, United States

Qualcomm is a global leader in semiconductor and telecommunications equipment, specializing in mobile technologies and innovations. Known for its Adreno GPUs, the company provides solutions enabling advancements in mobile gaming, AI, VR/AR, and autonomous driving. Qualcomm's cutting-edge technology and commitment to high-performance, power-efficient designs drive the evolution of mobile graphics and connectivity worldwide.