CPU SRAM Design Engineer - Sr Staff / Principal

Job Title

CPU SRAM Design Engineer — Sr Staff / Principal

Role Summary

Design, analyze and deliver custom SRAM and memory-related digital circuits for high-performance CPU products. The role owns schematic capture, simulation, verification, timing and model generation for SRAM/ register-file designs and works with CAD and Physical Design teams to meet performance, power and area targets.

Experience Level

Senior. Posting indicates experienced candidates (examples in the posting include preferred profiles with 10–12+ years); minimum qualification combinations in the source specify multi-year experience thresholds (see Education Requirements for degree-and-years combinations).

Responsibilities

Primary responsibilities for the role include:

• Develop custom digital circuits for high-speed and low-power SRAM and register-file designs.
• Schematic capture and design entry.
• Layout planning and supervision; provide guidance to layout teams.
• Functional verification and creation of memory logical models.
• Perform circuit simulation, Monte Carlo analysis and margin verification.
• Timing characterization and static timing analysis for memories.
• Generate deliverable collateral models and interact with CAD to ensure correct model generation.
• Collaborate with Physical Design to resolve memory PPA (performance, power, area) trade-offs.
• Contribute to modeling, DFT/BIST or memory analysis flow development as needed.

Requirements

Core must-have skills and experience; candidates should meet most of the must items and ideally several of the nice-to-have items.

Must-have

• Proven experience designing SRAM circuits and memory macros.
• Experience with industry-standard custom design tools and flows (design entry, simulation, verification, timing and power analysis flows).
• Circuit simulation experience, including Monte Carlo analysis and margin verification.
• Experience with static timing analysis for memories.
• Ability to produce deliverable models and documentation required for downstream teams (CAD, physical design).

Nice-to-have

• Strong knowledge of SRAM and register-file techniques and advanced custom circuit implementations.
• Experience with variation-aware simulation in FinFET and Nanosheet nodes and device fundamentals.
• Experience with custom memory layout designs and full memory analysis steps (layout guidance, electrical characterization, power analysis).
• Familiarity with memory logical models (Verilog), functional verification, BIST/DFT features and memory analysis flow development.
• Proficiency with tools such as NanoTime, Ansys EMIR, ESP-CV, Liberate (or similar memory/timing/power tools).

Education Requirements

Degrees and academic background found in the source: Bachelor's (BA/BS), Master's (MS) and PhD in Electrical Engineering, Computer Engineering, Computer Science or related technical fields. Example experience/degree combinations in the posting: BA/BS with ~12+ years (preferred listing), MS with ~10+ years (preferred), and the stated minimum qualification options: Bachelor's + 6+ years, Master's + 5+ years, or PhD + 4+ years of relevant engineering experience.

About the Company

Company: Qualcomm

Headquarters: San Diego, California, United States

Qualcomm is a global leader in semiconductor and telecommunications equipment, specializing in mobile technologies and innovations. Known for its Adreno GPUs, the company provides solutions enabling advancements in mobile gaming, AI, VR/AR, and autonomous driving. Qualcomm's cutting-edge technology and commitment to high-performance, power-efficient designs drive the evolution of mobile graphics and connectivity worldwide.