CPU–SoC Mask Layout Designer (Diploma level, contract)
Entry-level layout designer role within the Silicon Engineering Group (SiG) supporting CPU and SoC development. The role focuses on creating mask layouts, running layout verification and reliability checks, and contributing to floorplanning and power-grid design for next-generation silicon.
Works with internal and external stakeholders and follows established layout processes and design manuals. The role is eligible for a hybrid work model based at Intel's Penang site.
Entry-level — Diploma fresh graduates. This is a contract position suitable for candidates at the start of their engineering career.
Primary responsibilities include producing and verifying layout blocks and supporting silicon design flows.
Must-have qualifications and practical expectations for the role. Degree information is listed under Education Requirements below.
Diploma in Electrical and Electronic Engineering or a related technical field required. Positions are open to diploma fresh graduates; no alternative degree or equivalent-experience language was provided.
Company: Intel Corporation
Headquarters: Santa Clara, California, USA
Intel Corporation is a leading multinational technology company known for its innovative semiconductor solutions, including microprocessors, artificial intelligence accelerators, and memory products. Headquartered in the United States, Intel focuses on cutting-edge technology and a collaborative working environment, driving advancements in semiconductor manufacturing to meet global demands. The company emphasizes professional development and aims to shape the future of technology through groundbreaking designs.
