CPU-SoC Mask Layout Designer (Diploma-level, Contract)
Design and verify mask layouts for SOC/CPU blocks, perform layout-level checks (DRC, electromigration, IR drop, ESD, reliability), and support floorplanning and power-grid design for next-generation silicon. Work within a Silicon Engineering team and collaborate with internal and external stakeholders to deliver verified layout blocks for manufacturing.
Entry-level. Role is targeted at diploma fresh graduates starting their early career in semiconductor layout and mask design.
Primary duties include creating and verifying layout blocks and supporting the physical implementation flow.
Required skills, work conditions, and preferred knowledge. Degree details are listed under Education Requirements.
Diploma in Electrical and Electronic Engineering or a related field. Positions are open to diploma fresh graduates (Diploma-level candidates). No alternate degree equivalence or certification language was provided in the source.
Company: Intel Corporation
Headquarters: Santa Clara, California, USA
Intel Corporation is a leading multinational technology company known for its innovative semiconductor solutions, including microprocessors, artificial intelligence accelerators, and memory products. Headquartered in the United States, Intel focuses on cutting-edge technology and a collaborative working environment, driving advancements in semiconductor manufacturing to meet global demands. The company emphasizes professional development and aims to shape the future of technology through groundbreaking designs.
