CPU-SoC Mask Layout Designer
Design and verify mask layouts for CPU/SoC blocks used in Intel products. Work within a layout team in the Silicon and Platform Engineering Group to develop floorplans, power grid, bumps and perform required layout verification and reliability checks.
This role involves hands-on layout creation, running verification tool flows, troubleshooting layout and tool issues, and coordinating with internal and external stakeholders to meet project requirements.
Entry-level / early career. The posting indicates training will be provided; no specific years of experience required.
Primary responsibilities include layout creation, verification, and issue resolution for SOC/CPU projects.
Must-have technical skills and competencies for performing the role.
Diploma in Electronic and Electrical Engineering or a related major (with good CGPA) is required. Related technical fields are acceptable.
Company: Intel Corporation
Headquarters: Santa Clara, California, USA
Intel Corporation is a leading multinational technology company known for its innovative semiconductor solutions, including microprocessors, artificial intelligence accelerators, and memory products. Headquartered in the United States, Intel focuses on cutting-edge technology and a collaborative working environment, driving advancements in semiconductor manufacturing to meet global demands. The company emphasizes professional development and aims to shape the future of technology through groundbreaking designs.
