CPU RTL Engineer
AkeanaJob Title
CPU RTL Engineer
Role Summary
Design and implement CPU microarchitecture and RTL for high-performance processor products at an early-stage startup. Work in a small, cross-functional team to deliver execution units, caches and pipeline logic while optimizing timing, power and area.
Collaborate closely with Architecture, Verification and Physical Design teams and take ownership of significant design blocks.
Experience Level
Mid-level. Years of experience not specified.
Responsibilities
Primary responsibilities include:
- Develop RTL for CPU microarchitecture, including execution units and cache subsystems.
- Design and refine pipeline stages; drive timing closure and power/area optimizations.
- Work closely with architects, verification engineers and physical design to integrate and hand off designs.
- Own and deliver significant functional blocks within the CPU design.
Requirements
Must-have skills and preferred qualifications:
- Strong background in RTL design, micro-architecture development, pipelining, timing closure, and power/area optimization.
- Familiarity with processor architectures such as RISC-V, ARM, MIPS or x86.
- Ability to work effectively in a small startup team and take technical ownership.
- Nice-to-have: prior processor design experience; hands-on experience with execution units and cache subsystems.
Education Requirements
Not specified.
About the Company
Company: Akeana
Headquarters: Santa Clara, CA, USA
Akeana is a start-up specializing in processor design, with a team experienced in developing state-of-the-art products. Their expertise spans multiple architectures, including Risc-V, ARM, and x86, with backgrounds from prominent companies in the semiconductor industry. Funded by top-tier venture capitalists and industry leaders, Akeana focuses on innovative RTL design and micro-architecture development.
