CPU Power-Management Design Engineer

Job Title

CPU Power-Management Design Engineer

Role Summary

Design and implement clocking, reset, and power-management microarchitecture and RTL for high-performance, energy-efficient CPU and SoC IP. Collaborate with architecture, verification, physical implementation, and software teams to deliver configurable power-management solutions for RISC-V based SoCs.

Experience Level

Mid-level — typically requires 3+ years of relevant industry experience in CPU and SoC clocking, reset, and power-management design.

Responsibilities

Deliver microarchitecture, RTL, verification support, and integration for power, reset, and clocking subsystems.

• Define power-management requirements with architects and drive microarchitecture and RTL specifications.
• Architect and implement core clock distribution, dynamic clocking, clock gating, and reset control strategies.
• Design Power Management Unit (PMU) features, power state management, retention and sequencing for power-up/down.
• Implement DVFS and Di/dt mitigation strategies and other static/dynamic power reduction techniques.
• Perform initial sandbox verification and collaborate with verification teams to develop and execute test plans.
• Work with physical implementation teams to meet frequency, area, and power targets.
• Support software teams to enable and optimize power-management features.

Requirements

Must-have technical skills and experience required for successful performance in this role.

• 3+ years of industry experience in CPU and SoC clocking, reset, and power-management logic design.
• Proven experience in high-performance, energy-efficient CPU and SoC designs from architecture through tapeout.
• Expertise in clocking and reset design, clock distribution, clock gating, and clock domain crossing strategies.
• Experience with PMU design, power-state definition/management, retention strategies, and power sequencing.
• Experience with DVFS, Di/dt mitigation, and power-aware simulation.
• Understanding of DFT, MBIST, debug and error-handling in CPU designs.
• Proficiency in RTL design (Verilog, SystemVerilog, or VHDL) and familiarity with RTL quality checks (linting, CDC, RDC).
• Strong attention to detail, teamwork, and ability to document and communicate designs clearly.
• Familiarity with at least one object-oriented or functional programming language.

Nice-to-have:

• Experience with AMBA protocols (AXI, AHB, APB) and AMBA Low Power protocol interfaces.
• Experience with hardware DSLs or generators (Scala/Chisel, Bluespec) and configurable-hardware flows.
• Experience with Spyglass or similar lint/quality tools; familiarity with Git, GitHub, Jira, Confluence.
• Knowledge of the RISC-V architecture.

Education Requirements

BS or MS in Electrical Engineering, Computer Engineering, Computer Science, or a related technical discipline — or equivalent practical industry experience.

About the Company

Company: SiFive

Headquarters: San Mateo, California, United States

SiFive is a pioneering company in the RISC-V ecosystem, focused on transforming the future of computing by delivering high-performance, data-intensive RISC-V solutions. Their compute platforms empower leading technology firms to innovate across various markets, including AI, machine learning, and automotive sectors. SiFive is recognized for its commitment to ongoing innovation and fostering collaboration among talented teams, impacting lives by enabling advanced chip design.