CPU Power-Management Design Engineer

Job Title

CPU Power-Management Design Engineer

Role Summary

Design microarchitecture and RTL for power management, reset, and clocking systems for RISC-V CPU cores and SoC IP. Collaborate with architecture, verification, physical implementation, and software teams to deliver configurable, high-performance, energy-efficient hardware IP.

Work in a fast-paced product environment to move hardware from architecture through tapeout and production-quality IP delivery.

Experience Level

Mid-level — typically requires 3+ years of industry experience in CPU/SoC clocking, reset, and power-management logic design.

Responsibilities

Primary responsibilities include microarchitecture, RTL implementation, verification support, and collaboration with cross-functional teams to meet frequency, area, and power targets.

• Define power-management requirements with architecture and system teams.
• Architect, design, and implement clocking, reset, and power-management solutions (PMU, power states, sequencing).
• Create microarchitecture specifications and documentation to share design intent and implementation details.
• Perform initial sandbox verification and work with verification engineers to develop and execute verification plans.
• Collaborate with physical implementation teams to implement and optimize designs for timing, area, and power.
• Work with software teams to enable and optimize power-management features and firmware interfaces.

Requirements

Must-have technical skills and experience:

• 3+ years recent industry experience in CPU and SoC clocking, reset, and power-management logic design.
• Expertise in clock distribution, clock gating, dynamic clocking, clock-domain crossing strategies, reset control, and power sequencing.
• Experience with power-management units (PMU), power-state definition/management, DVFS, retention, and Di/dt mitigation strategies.
• Experience with power-aware simulation, DFT/MBIST, debug and error-handling in CPU designs.
• Proficiency in RTL design using Verilog or SystemVerilog or VHDL and familiarity with RTL quality checks (Lint, CDC, RDC). Spyglass experience is a plus.
• Background delivering CPU or SoC designs from architecture through tapeout; strong documentation and collaboration skills.
• Familiarity with at least one object-oriented or functional programming language.

Preferred / Nice-to-have:

• Experience with AMBA protocols (AXI, AHB, APB) and AMBA Low Power Protocol interfaces (P-channel, Q-channel).
• Experience with Scala/Chisel, Bluespec, or other hardware DSLs for configurable hardware generators.
• Knowledge of RISC-V architecture and experience with Git/GitHub, Jira, Confluence.

Education Requirements

BS or MS in Electrical Engineering, Computer Engineering, Computer Science, or a related technical discipline — or equivalent practical experience.

About the Company

Company: SiFive

Headquarters: San Mateo, California, United States

SiFive is a pioneering company in the RISC-V ecosystem, focused on transforming the future of computing by delivering high-performance, data-intensive RISC-V solutions. Their compute platforms empower leading technology firms to innovate across various markets, including AI, machine learning, and automotive sectors. SiFive is recognized for its commitment to ongoing innovation and fostering collaboration among talented teams, impacting lives by enabling advanced chip design.