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CPU Physical Design Engineer, Staff

Qualcomm
September 10, 2026
Full-time
On-site
Hyderabad, Telangana, India
Physical Design Jobs, Level - Senior

Job Title

CPU Physical Design Engineer, Staff

Role Summary

Join the Snapdragon CPU physical design team in Hyderabad to implement and optimize high-performance CPU blocks for advanced SoCs in sub-10nm technologies. The role focuses on RTL-to-GDSII implementation, PPA (performance, power, area) optimization, timing closure, and close collaboration with synthesis, STA, power and verification teams.

Experience Level

Senior - typically requires 7+ years of professional experience in ASIC physical design and high-performance CPU implementation.

Responsibilities

Primary responsibilities cover block-level physical implementation and delivery of PPA goals.

  • Own and drive block-level physical design from RTL/netlist to GDSII.
  • Perform place & route, timing closure, power optimization, physical verification, and signoff.
  • Develop and optimize implementation methodologies, flows, and recipes to improve PPA.
  • Create and execute experiments to evaluate implementation strategies and improve QoR.
  • Analyze and track implementation metrics to guide design decisions.
  • Collaborate with RTL design, synthesis, STA, power, thermal, and verification teams.
  • Debug and resolve issues related to timing, power, congestion, and physical verification.
  • Contribute to automation and flow enhancements using scripting.

Requirements

Key technical must-haves and additional preferred skills.

  • Must-have: 7+ years of experience in ASIC physical design with strong RTL-to-GDSII implementation expertise.
  • Proven experience with place & route, timing closure, power optimization, and signoff flows.
  • Strong debugging and problem-solving skills for timing, power, and physical verification issues.
  • Proficiency with scripting for automation (Tcl, Python, Perl).

Nice-to-have:

  • Hands-on experience with Cadence Innovus and/or Synopsys Fusion Compiler.
  • Experience with STA tools (PrimeTime, Tempus) and SDC constraint generation and debugging.
  • Experience with multi-power-domain designs and UPF/CPF implementation.
  • Knowledge of low-power design techniques, IR/EM analysis, signal/power integrity.
  • Experience on advanced process nodes (7nm and below) and high-frequency CPU implementations.
  • Familiarity with formal verification tools (Formality, Conformal) and Verilog.

Education Requirements

Bachelor's, Master's, or PhD in Computer Science, Electrical/Electronics Engineering, Computer Engineering, or a related engineering field are listed as acceptable academic backgrounds.


About the Company

Company: Qualcomm

Headquarters: San Diego, California, United States

Qualcomm is a global leader in semiconductor and telecommunications equipment, specializing in mobile technologies and innovations. Known for its Adreno GPUs, the company provides solutions enabling advancements in mobile gaming, AI, VR/AR, and autonomous driving. Qualcomm's cutting-edge technology and commitment to high-performance, power-efficient designs drive the evolution of mobile graphics and connectivity worldwide.

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Date Posted: 2026-09-10