CPU Physical Design Engineer

Job Title

CPU Physical Design Engineer

Role Summary

Design and implement CPU core physical layouts from RTL to GDS for high-performance, power-efficient processors. Work on full physical implementation flow and verification, collaborating with logic, circuit, architecture, design automation teams, and EDA vendors.

Experience Level

Entry / early career. Typical candidate has roughly 1–2+ years of relevant industry experience; master's degree holders with 1+ year also considered.

Responsibilities

Execute and sign off physical implementation tasks for CPU blocks and full chips.

• Perform RTL-to-GDS physical design: synthesis, floorplanning, placement, routing, clock tree synthesis, and GDS generation.
• Perform static timing analysis, power analysis, noise/reliability analysis, and power/clock distribution design.
• Run verification and signoff flows: formal equivalence, DRC/LVS, electrical rule checks, static/dynamic power integrity, and layout checks.
• Troubleshoot timing and physical issues; optimize designs for power, frequency, and area.
• Collaborate with architecture, logic, circuit, and EDA vendor teams to improve tool flows and methodologies.

Requirements

Must-have technical skills and experience; preferred items listed separately.

• Experience with digital logic synthesis and physical implementation tools (examples: Synopsys, Cadence) including synthesis, place-and-route, and timing closure.
• Experience with static timing and power (PV) convergence and related analysis flows.
• Experience in physical verification workflows: formal equivalence, DRC/LVS, and noise verification flows.
• Practical TCL scripting skills for automation and flow integration.
• Demonstrated problem solving on timing violations and implementation issues at block or chip level.

Nice-to-have / Preferred:

• Knowledge of floorplanning, routing techniques, and clock distribution best practices.
• Experience with CPU-level timing analysis, generating and verifying timing constraints, and working with clocking/full-chip teams.
• Experience participating in tape-out on advanced process technologies.
• Familiarity with RTL-to-GDS methodologies and full signoff methodologies.

Education Requirements

Bachelor's in Computer Engineering, Electrical Engineering, or related field (typical requirement: B.S. + ~2 years' relevant experience) or a Master's degree in those fields (typical: M.S. + ~1 year). Candidates with equivalent practical industry experience, internships, or relevant coursework/research will be considered.

About the Company

Company: Intel Corporation

Headquarters: Santa Clara, California, USA

Intel Corporation is a leading multinational technology company known for its innovative semiconductor solutions, including microprocessors, artificial intelligence accelerators, and memory products. Headquartered in the United States, Intel focuses on cutting-edge technology and a collaborative working environment, driving advancements in semiconductor manufacturing to meet global demands. The company emphasizes professional development and aims to shape the future of technology through groundbreaking designs.